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Evaluation of Branch Prediction Methods in Commercial Applications and their OS Impacts

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kacy
16 diapositives · 303 Views · Sep 01, 2014

This study analyzes various branch prediction methods using traces from commercial applications. It discusses the effectiveness of different techniques, with a focus on SPECmark test suite traces and the challenges posed by multitasking operating systems. The paper highlights the distinction between static and dynamic branches, examines the complexities of branch target buffers, and explores the implications of different instruction sets, particularly for the IBM ESA/390. The findings underscore that while significant progress has been made, the superiority of any method remains unclear.

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Evaluation of Branch Prediction Methods in Commercial Applications and their OS Impacts
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  1. Evaluation of branch-prediction methods on traces from commercial applications R.B. Hilgendorf, G. J. Helm, W. Rosenstiel

  2. Progress? • Significant, but it is still not clear which, if any, of the currently advocated methods is superior. • SPECmark test suite traces are often used • The gcc trace seems to be the most difficult for branch-prediction

  3. Effect of Multitasking OS • Increases the activity in a processor • For the IBM ESA/390 series there exists a completely different set of traces that show the involvement of the OS

  4. Trace Description • T1: Transaction processing such as database queries in warehouse management • T2: Interactive usage in program development. Searching, compiling. • T3: Transaction processing from tasks such as hotel reservations. • T4: Commercial batch jobs.

  5. Distinction • Static branches. Found in the binary program. Eliminate duplicates. • Dynamic branches. Occur when running a program. Found in the trace. • The term dynamic instructions means the total number of instructions in the trace.

  6. The ESA/390 Instruction Set • About 17 different branch instructions • The majority of these in the traces receive their target address • From a general purpose register • A base register plus an index register plus a constant • Coding the index register as zero will force even unconditional branches never to branch • When using a certain mask all branches will take

  7. Continued • Using only the opcode of a branch will not provide enough information • A further obstacle is that there is no distinct call and no return instruction

  8. Branch Target Buffer • Is intended to contain the target address for each branch and prediction information • Normally addressed using the instruction address of the branch instruction • Various techniques fold the complete address space into a usable BTB of affordable size

  9. Continued • If a branch is not in the BTB, that counts as a miss • First or cold misses plus misses due to replacement • For small BTBs replacement misses dominate

  10. Continued • Large BTB • BTB stores effective addresses, not absolute addresses. • After a task switch part of the BTB content is useless, or worse, conterproductive • Instructions that are not even branches may be predicted

  11. Continued • Modern processors generally fetch more than a single instruction per cycle • An address range must be tested for a branch • put block addresses in the table • Not preferable

  12. Local History

  13. Global History • One large history register • Addresses a table of two-bit saturation counters • Incremented when a branch is taken, decremented when a branch is not taken, but 3++ = 3 and 0-- = 0 • Best! • A path is used to predict!

  14. Moving Targets • We have assumed so far that • The target address in the BTB was correct • We only have to worry about taken/not taken • Some branches may have different target addresses • Return • Indirect branches • Case statement, jump tables, computed go-tos

  15. Moving Targets (contd) • If you have specific call and return instructions, you can use a return stack to get 100% prediction on returns. • The ESA/390 does not have such instructions (neither does SPARC) • A branch can be used as a call or a return

  16. Continued • An identification stack into which each possible call is written with its target and return address • A return cache that receives new entries from the IS when the stored RA matches the target address of a possible return.