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Exploring the ESW Paradigm: Enhancements in Instruction-Level Parallelism and Resource Optimization

The ESW paradigm highlights advancements in instruction-level parallelism (ILP) with a focus on decentralized resources and minimized communication costs. The approach identifies the limitations of centralized resources and seeks to optimize execution through a dataflow and sequential model. It emphasizes speculative memory disambiguation and introduces small dynamic windows to enhance scalability and efficiency. Leveraging a custom simulator with MIPS architecture, this framework reveals promising results in both in-order and out-of-order execution, aiming for a more effective use of registers and instruction handling.

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Exploring the ESW Paradigm: Enhancements in Instruction-Level Parallelism and Resource Optimization

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  1. The ESW Paradigm Manoj Franklin & Guirndar S. Sohi 05/10/2002

  2. Observations • Large exploitable ILP, theoretically • Close instructions dependent; parallelism possible further down stream • Centralized resources is bad • Minimizing comm cost is important

  3. What about others? • Dataflow model + most general • unconventional PL paradigm • comm cost can be high • SS, VLIW (sequential) + temporal locality • large centralized HW • compiler too dumb • not scalable • ESW = dataflow + sequential

  4. Design Goals • Decentralized resources • Minimize wasted execution • Speculative memory address disambiguation • realizability Replace large dynamic window with many small ones

  5. How it works • Basic window • Single entry, loop-free, call-free block • Equal, superset or subset of basic block • Execute basic windows in parallel • Multiple independent stages • Complete with branch prediction, L1 cache, reg file…etc.

  6. Dist Inst Supply Optimization: Snooping on L2-L1 Cache traffic

  7. Dist Inter-Inst Comm • Architecture: • dist. future file • create/use masks for dep. check • Observation: • Register use mostly within basic block • The rest in subsequent blocks

  8. Dist DMem System • Problem: • Addr. space large, can’t create/use mask • Need to maintain consistency between multiple copies • Solution: ARB

  9. ARB • - Bits cleared upon commit • Restart stages when dependency violated • When load, forward values from ARB if already exists Q. What happens when ARB’s full?

  10. Simulation Environment • Custom simulator using MIPS R2000 pipeline • Up to 2 inst fetch/decode/issued/ per IE • Up to 32 inst per basic window • 4K word L1 cache, 64KB L2 DM Cache (100% hit rate, what??) • 3-bit counter branch prediction

  11. Results • Optimizations: • Moving up instruction • Expand basic window (in eqntott and expresso) Basic window <= basic block But is 100% cache hit rate reasonable?

  12. Discussion • Compare this to CMP? RAW? • Does the trade-off strike a balance?

  13. New Results (1) In order execution

  14. New Results (2) Out of order execution

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