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Comprehensive Overview of Single and Multicycle Datapath for MIPS Architecture

This document provides an in-depth exploration of the single cycle and multicycle datapath architectures used in MIPS (Microprocessor without Interlocked Pipeline Stages). It covers the fundamental operations of instruction fetching, decoding, execution, and memory access, along with exception and interrupt handling. Additionally, it elucidates the specific roles of components such as ALU, registers, control logic, and multiplexers in processing various instruction types, ensuring a solid understanding of the MIPS architecture's functionality and efficiency.

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Comprehensive Overview of Single and Multicycle Datapath for MIPS Architecture

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  1. mux ADD ADD +4 shift 2 BRANCH CTRL rs PC R1 R Data 1 zero addr rt R2 ALU addr instr R Data 2 mux mux r data rd WR INSTR MEM w data W Data DATA MEM Single Cycle Datapath immed ALU CTRL sign extend 16 32 op

  2. Multicycle Datapath jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data MR fetch decode execute (1..3) REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  3. Multicycle with Exception/Interrupt Handling jump addr shift 2 handler addr zero rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data overflow rd MEMORY PC - 4 W Data MR EPC to? REGISTERS immed sign extend shift 2 CAUSE 00 01 10 11 op fctn shamt CONTROL to?

  4. Pipelined Datapath +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend IF ID EX MEM WB

  5. add rd, rt, rs: Fetch +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data Instruction Fetch: Load IR, PC = PC + 4 w data Data Memory sign extend IF Register Contains IR and PC, and other values

  6. add rd, rt, rs: Decode +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend ID register contains A, B, and other values Instruction Decode: Load data1, data2 into A, B (part of ID)

  7. add rd, rt, rs: Execute +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Execute: sum of A, B into ALUout (part of EX)

  8. add rd, rt, rs: MEM +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend MEM: (no memory access) save ALU result in MEM

  9. add rd, rt, rs: WB +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Write Back: write sum to register rd

  10. sw rt, offset(rs): Fetch +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend

  11. sw rt, offset(rs): Decode +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend ID gets rs, rt, and immed+sign ext

  12. sw rt, offset(rs): Execute +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend EX gets rs+offset, and rt

  13. sw rt, offset(rs): MEM +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Write Data Memory [address] with rt value; nothing of interest in WD Data Memory sign extend

  14. sw rt, offset(rs): WB +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory Registers not written in this instruction sign extend

  15. A program fragment with 6 instructions 1. add r1, r2, r3 2. sw r4, 2232 ( r5 ) 3. addi r6, 55 4. lw r7, 1001 (r8) 5. bneq r7, r6, -3 6. add r1, r7, r0

  16. A program fragment with 6 instructions 1. add r1, r2, r3 2. sw r4, 2232 ( r5 ) 3. addi r6, 55 4. lw r7, 1001 (r8) 5. slti r7, r6, -3 6. add r1, r7, r0

  17. Six instructions 1,2,3,4,5,6: Step 1 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Fetch 1

  18. Six instructions 1,2,3,4,5,6: Step 2 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Fetch 2 Decode 1

  19. Six instructions 1,2,3,4,5,6: Step 3 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Fetch 3 Execute 1 Decode 2

  20. Six instructions 1,2,3,4,5,6: Step 4 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Decode 3 Execute 2 Mem 1 Fetch 4

  21. Six instructions 1,2,3,4,5,6: Step 5 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Fetch 5 Decode 4 Execute 3 Mem 2 (sw) WB 1 (add)

  22. Six instructions 1,2,3,4,5,6: Step 6 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Execute 4 Mem 3 (addi) Fetch 6 Decode 5 WB 2 (sw: no write)

  23. Six instructions 1,2,3,4,5,6: Step 7 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Mem 4 (lw) Execute 5 Decode6 WB 3 (addi)

  24. Six instructions 1,2,3,4,5,6: Step 8 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Mem 5 (slti) Execute 6 WB 4 (lw)

  25. Six instructions 1,2,3,4,5,6: Step 9 +4 add add Registers shift mux addr read1 PC read2 data1 out write ALU mux addr mux data2 r data Instruction Memory w data w data Data Memory sign extend Mem 6 (add) WB 5 (slti)

  26. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data add rd, rs, rt fetch: load ir, pc=pc+4 decode execute MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  27. Multicycle Datapath jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data MR fetch decode execute REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  28. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data add rd, rs, rt fetch decode:load A,B registers execute MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  29. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data add rd, rs, rt fetch decode execute (2 cycles) load alu out; load register MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  30. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data bne rs, rt, addr fetch: load IR, pc=pc+4 decode execute MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  31. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd bne rs, rt, addr fetch decode: load A B, aluout = immediate (extendx2)+pc execute MEMORY W Data MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  32. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd bne rs, rt, addr fetch: decode: execute: (1 cycle) compare A, B (holding rs, rt); if neq, load pc with aluout (holding branch addr) MEMORY W Data MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  33. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data lw rt, offset ( rs) fetch: load IR, pc=pc+4 decode execute MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  34. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data lw rt, offset ( rs) fetch decode: load A B; offset is ready execute MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  35. jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data lw rt, offset ( rs) fetch decode execute: (3 cycles): load aluout with addr, load mr with data, load register rt MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  36. Multicycle Datapath jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data Try these: sw rt, off(rs) j addr andi rd,rs,rt MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  37. Multicycle Datapath z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data MR REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

  38. R-Format: add, slt, sll rs PC R1 R Data 1 addr rt R2 ALU instr R Data 2 WR rd INSTR MEM DATA MEM W Data fctn ALU CTRL op shamt

  39. mux ADD ADD +4 shift 2 BRANCH CTRL rs PC R1 R Data 1 zero addr rt R2 ALU instr R Data 2 WR INSTR MEM DATA MEM W Data immed ALU CTRL sign extend 16 32 op I-Format bne

  40. I-Format lw, sw rs PC R1 R Data 1 zero addr rt R2 ALU addr instr R Data 2 R Data mux WR INSTR MEM W Data W Data DATA MEM immed ALU CTRL sign extend 16 32 op

  41. mux ADD ADD +4 shift 2 BRANCH CTRL address PC R1 R Data 1 zero addr R2 ALU instr R Data 2 WR INSTR MEM DATA MEM W Data ALU CTRL op J-Format

  42. Multicycle Datapath jump addr shift 2 z rs addr R1 R Data 1 A PC rt ALU alu out R2 IR data R Data 2 B +4 WR w data rd MEMORY W Data MR fetch decode execute REGISTERS immed sign extend shift 2 op fctn shamt ALU CTRL

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