1 / 9

Advanced VLSI Design: Optimizing Core Ratios for Timing and Leakage Control

This document addresses advanced VLSI design techniques focusing on the influence of core height/width ratios on design performance. It explores methods to optimize designs for timing and leakage concerns, particularly at high frequencies (up to 300 MHz). The report discusses necessary changes in power planning strategies, including ring and stripe configurations, to mitigate increased leakage resulting from these optimizations. The layout results with pads are presented, showcasing the impact of these strategies. Thank you for your attention.

kami
Télécharger la présentation

Advanced VLSI Design: Optimizing Core Ratios for Timing and Leakage Control

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Phase 4 – BjoernKonieczek Applied VLSI Design

  2. Design Approach G R B R G B Y Cb Cr

  3. Possible Optimizations • Influence of Core height/width ratio • Optimize Design for Timing/Leakage • Make Changes in Power Plan (Ring/Stripes)

  4. 1. Influence of height/width ratio

  5. 2. Optimization for Timing/Leakage • High frequencies possible (up to 300 MHz) • But results in a drastic increase of leakage

  6. Resulting Layout

  7. Layout withPads

  8. Results

  9. Thank YOU For YOUR ATTENTION

More Related