Real-Time Canny Edge Detection Parallel Implementation for FPGAs

1. 17th IEEE International Conference on Electronics, Circuits, and Systems ICECS 2010 – Athens - Greece Real-Time Canny Edge Detection Parallel Implementation for FPGAs Christos Gentsos1, Calliope-Louisa Sotiropoulou1, Spiridon Nikolaidis1 and Nikolaos Vassiliadis2 1Electronics Lab, Physics Dept., Aristotle Univ. of Thessaloniki, Greece 2Micro2Gen Ltd. , NCSR Demokritos, Greece

2. Outline • Motivation • Canny Algorithm • Proposed Canny Implementation • Simulations – Results • Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

3. Outline • Motivation • Canny Algorithm • Proposed Canny Implementation • Simulations – Results • Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

4. Motivation • Necessity of Edge Detection • First step in many computer vision algorithms • Identification of sharp discontinuities in an image • Why use the Canny algorithm • Good performance in images contaminated by noise • The need for Real-Time/High Throughput Implementation • Multiplication of camera resolutions in recent years • Real-time applications • The performance of modern FPGA devices • Powerful, efficient, availability of memory resources C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

5. Outline • Motivation • Canny Algorithm • Proposed Canny Implementation • Simulations – Results • Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

6. Canny Algorithm SmoothingFilter Calculation of gradient Localization Elimination of spurious responses C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

7. Outline • Motivation • Canny Algorithm • Proposed Canny Implementation • Simulations – Results • Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

8. Implementation Approach • Introduction of a 4-pixel parallel computation design • Pipelined architecture using on-chip BRAM memories for caching • Very efficient design with the same memory requirements as with a design without parallelism • In addition, complex arithmetical operations were substituted with shifts and additions/subtractions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

9. Pipeline Implementation • Exploitation of minimum buffering before starting the computation C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

10. Gaussian Smoothing • 5 x 5 convolution • Introducing 4-pixel parallelism • Substitution of the multiplications and divisions with shifts additions and subtractions 25 pixels 40 pixels C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

11. Gaussian Smoothing C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

12. Gaussian Smoothing • Exploitation of on-chip BRAMS • Use of one BRAM to accommodate one image line aligned in 4-pixel words • Each BRAM has a size of image width / 4 x 32 bits (grayscale) C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

13. Gaussian Smoothing • Start of calculations  As soon as the first 2 lines of the cache are filled • All non-existing lines and columns of pixels necessary for the calculations are considered to be black C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

14. Sobel Gradient Calculation • 3 x 3 convolution • Introducing 4-pixel parallelism • Substitution of the multiplications and divisions with shifts additions and subtractions • Use of fixed point arithmetic 9 pixels 18 pixels C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

15. Sobel Gradient Calculation • Start of calculations  As soon as the first line of the cache are filled • All non-existing lines and columns of pixels necessary for the calculations are considered to be black C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

16. Non Maximum Suppression • Same principles as in Sobel Gradient Calculation • Requires the 3 x 3 neighboring pixels 9 pixels 18 pixels C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

17. Double Thresholding and Hysterisis • Double Thresholding is a double comparator • No caching required for this stage • Hysterisis normally requires the 3 x 3 neighboring pixels • Reduced to 4 neighboring pixels • Second pass in the opposite direction C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

18. Hysterisis Block C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

19. Outline • Motivation • Canny Algorithm • Proposed Canny Implementation • Simulations – Results • Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

20. Simulations - Results • Synthesis results for 3 different FPGAs C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

21. Simulations - Results • Timing results for Spartan-6 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

22. Outline • Motivation • Canny Algorithm • Proposed Canny Implementation • Simulations – Results • Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

23. Conclusions • Real-time canny implementation • Parallel architecture with 4-pixel calculation • Increased throughput without increased need for memory resources • 240 frames per second achieved for 1Mpixel images on a Spartan-3E with 28% of the area • 580 frames per second on a Virtex-5 • 396 frames per second on a Spartan-6 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

24. Acknowledgement The research activities that led to these results, were co-financed by Hellenic Funds and by the European Regional Development Fund (ERDF) under the Hellenic National Strategic Reference Framework (ESPA) 2007-2013, according to Contract no. MICRO2-49-project LoC. Thank you very much for your attention! C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab