1 / 32

On behalf of Genoa group

BoNus RTPC DAQ Upgrade. On behalf of Genoa group. Outline. Motivation Current DAQ system overview Hardware architecture Trigger and Data size performances calculation New RCU Block Diagram and architecture Trigger and Data size performances calculation Board available Optical link

kaylee
Télécharger la présentation

On behalf of Genoa group

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. BoNus RTPC DAQ Upgrade. On behalf of Genoa group Genova, 22 October 2008

  2. Outline • Motivation • Current DAQ system overview • Hardware architecture • Trigger and Data size performances calculation • New RCU • Block Diagram and architecture • Trigger and Data size performances calculation • Board available • Optical link • D-RORC architecture • Link performances • Software • Low Voltage • Material procurement • To be done…. Genova, 22 October 2008

  3. Motivation • Are the Event Data Size (EDS) and/or the Trigger Event Rate (TER) increasable ? • As configured the current DAQ system provides readout of ~1kB event at a rate of about 500 Hz. Genova, 22 October 2008

  4. Current DAQ system • The electronic DAQ system is based on ALICE TPC readout cards. • It follows the RTPC structure split in two independent and identical sectors. Left and Right. • Boards per sector: • 104 of JLAB 16 chs preamplifier Tx/Rx cards • Capable of driving the RTPC signals across a ~6m long ribbon cable. • 13 Carrier FrontEndCards (FECs) • 128 chs/FEC  1664 channels/sectors • Custom ALTRO 40 bits data bus and control bus backplane • U2F readout controller Genova, 22 October 2008

  5. Current Read Out Setting • Analog input ADC sampling rate and size • Ts = 114 ns  Fs  8.8MHz; 10 bits ALTRO ADC. • Event Data Size depends by: • Number of samples • Ns = 100 samples/channel interval window 11.4 s • 15 pre-trigger samples  1.7s • 85 post-trigger samples  9.7s • Number of Channels over threshold • Now 1% of a whole RTPC module after zero suppression • 1% of (13 FECs * 128 chs) = 17 channels/event Genova, 22 October 2008

  6. Current Read Out Setting • Trigger Event Rate depends by: • ALTRO bus Bandwidth (theoretic 40MHz * 40 bit = 200MB/s) • Event Data Size • Event buffer depth • Readout clock frequency • Readout protocol dead time • Due to ALTRO  RCU handshake • Due to empty channels • RCU-USB2  DAQ PC Bandwidth (theoretic 60MB/s) • Bulk mode protocol • Endpoints (#2 and #6) • Data block size  1024B • Header and Trailer dead time Genova, 22 October 2008

  7. Current FEE overview #13 DETECTOR Carrier Front End Card (128 Channels) #1 L1 L2 drift region 7.6ms 8 CHIPS (16 CHs / CHIP) Capton cable 8 CHIPS (16 CHs / CHIP) ALTRO gating grid Digital Circuit Tx Rx USB PASA U2F ADC RAM anode wire FEC pad plane 1664 PADS CUSTOM IC (CMOS 0.35mm) CUSTOM IC (CMOS 0.25mm ) 60MB/s 6m ribbon cable Custom Data and Control Backplane 200MB/s CSA SEMI-GAUSS. SHAPER • BASELINE CORR. • TAIL CANCELL. • ZERO SUPPR. 10 BIT < 25 MHz MULTI-EVENT MEMORY GAIN = 12 mV / fC FWHM = 190 ns Genova, 22 October 2008

  8. OPA OPA T0 Noise < 103 e Cf Tp OPA Cd T0 Q integrator with continuos reset PZ differentiator 4 integrators (RC)4 diff output amplifier charge sensitive amplifier 4th order semi-gaussian shaper • Gain: 12mV / fC • FWHM: 190ns • Noise: < 1000 • Shaping time: 100ns • Peaking time: 190ns • Power: < 20mW / ch Q/Cf CSA OA SA Pre-Amplifier Shaping Amplifier (PASA) Genova, 22 October 2008

  9. ALTRO Block Diagram Data Processor • Correction of: • Slow drifts and systematic effects • Non-systematic effects • Tail filtering • Data compression TSA1001 Memory • 40-bit back • linked format • Channel address • Time stamp 10-bit 25 MSPS 5 kbyte (1024*40bit) 4 or 8 buffers Input Signal 0 L1: acquisition L2: event freeze Trigger signals 40MHz - 40-bit wide bus Bandwidth: 200 Mbyte/s Readout bus Genova, 22 October 2008

  10. Zero Suppression • The ALTRO zero suppression features, provides extensive data compression capabilities. • With RTPC detector up to 99% of readout data eliminated. Basic detection scheme Feature extraction Glitch filter Genova, 22 October 2008

  11. Data Format Multi Event Buffer Back linked data block Data formatting procedure Genova, 22 October 2008

  12. Multi Event Buffer Multi Event Buffer operation Multi Event Buffer structure Genova, 22 October 2008

  13. Current Max Event Rate estimation • Assuming that: • 100 samples/ch, and 40MHz (25ns) Readout clock. • 13 FECs@128chs  1664chs/sector and 1% of 1664 chs fired = 17chs • ALTRO MEB  RCU FIFO • DataBlockSize/ch = 100samples : 4 = 25 words (40bits long) • TotalDBS/ch = DBS/ch + 2 [(time + block length) + trailer] = 27 words • RO_time/ch = 700ns(ch handshake) + (25ns * 27words) = 1.4s • RO_time/chs_empty = [700ns + 25ns(ch trailer)] * (1664 - 17)  1.2ms • RO_time/branch = 1.2ms + (1.4s * 17)  1.22ms • Max_Event_Rate = 1/RO_time/branch  820Hz Genova, 22 October 2008

  14. Current Branch Bandwidth estimation • TDBS/ch expressed in byte  (25 + 2) * 5= 135B • Data_Volume_Fired_Chs = 17chs * 135B  2.3kB/event • Data_Volume_Empty_Chs = (1664-17) * 5B (trailer)  8.2kB/event • Total DV = 2.3kB + 8.3kB = 10.5kB/event • BranchBWmin = 820Hz * 10.5kB  8.6MB/s • ALTRO bus dead time evaluated as dummy 40bits data words  ADT = 700ns/25ns = 28 words • EffectiveALTRObusBW = (40MHz * 5B) * (TDBS/ (TDBS+ADT)) • 200MB/s * [27 / (27+28)] = 98MB/s >> BBWmin = 8.6MB/s Genova, 22 October 2008

  15. DAQ with new Read Out Control board Rx - PASA - ALTRO FEC 128 ch 13 Front-end bus ( 200 MB / s ) FEC 128 ch 2 RCU FEC 128 ch 1 Data Proc. and Memory Tx DDL ( 200 MB/s ) Bus controller ( conf. & R/O ) DETECTOR DAQ int. (DDL-SIU) DCS ( 1 MB/s ) FEC 128 ch 12 BOARD Controller DCS int. (Ethernet) Local Monitor and Control TTC optical Link (Clock, L1 and L2 ) Trigger and Timing circuit Trigger int. (TTC-RX) FEC 128 ch 2 Control Network (I2C-serial link) FEC 128 ch 1 Genova, 22 October 2008

  16. RCU features • Interleaved ALTRO data memories • Manage optical Serial Interface Unit • Clock, Trigger distribution to FEC • Data formatting and transfer to DAQ • Fast Active Channel List handling • Sparse Readout algorithm • Hit List compilation • 3 trigger sources • LHC TTC system • Software (debugging) • Hardware • Safety module monitoring • Linux Controller • FEC settings • Firmware update, check and reload • Ethernet Genova, 22 October 2008

  17. New Max Event Rate estimation SPARSE READOUT • Assuming that: • 100 samples/ch, and 40MHz (25ns) Readout clock. • 13 FECs@128chs  1664chs/sector and 1% of 1664 chs fired = 17chs • ALTRO MEB  RCU FIFO • DataBlockSize/ch = 100samples : 4 = 25 words (40bits long) • TotalDBS/ch = DBS/ch + 2 [(time + block length) + trailer] = 27 words • RO_time/ch = 700ns(ch handshake) + (25ns * 27words) = 1.4s • RO_time/branch = (1.4s * 17) + 120s(hit list)  143.8 s • Max_Event_Rate = 1/RO_time/branch  7kHz Genova, 22 October 2008

  18. New Branch - DDL Bandwidth estimation SPARSE READOUT • TDBS/ch expressed in byte  (25 + 2) * 5= 135B • Data_Volume_Fired_Chs = 17chs * 135B  2.3kB/event • Optical link Data Format Header: 32B/event (8 words of 32 bits) • Optical link Data Format Trailer: 40B/event (10 words of 32 bits) • Total DV = 2.3kB + 72B  2.4kB/event • BranchBWmin = 7kHz * 2.3kB  16MB/s (No Header and Trailer overhead) • ALTRO bus dead time evaluated as dummy 40bits data words  ADT = 700ns/25ns = 28 words • EffectiveALTRObusBW = (40MHz * 5B) * (TDBS/ (TDBS+ADT)) • 200MB/s * [27 / (27+28)] = 98MB/s >> BBWmin = 16MB/s • DDL_BWmin = 7kHz * 2.4kB  17MB/s • EffectiveDDLbusBW = 200MB/s * ((DBS*5)/ ((DBS*5)+Header+Trailer) • 200MB/s * [128 / (128+32+40)] = 128MB/s >> DDL_BWmin = 17MB/s • DBS*5 rounded to 32 bits word. 25*5B/4B = 31.25;  rounded to 128B/4B = 32 Genova, 22 October 2008

  19. Motivation • Are the Event Data Size (EDS) and/or the Trigger Event Rate (TER) increasable ? Yes, up to 7kHz at the same sampling rate (114ns  8.8MHz) and samples number (100). • As configured the current DAQ system provides readout of ~1kB event at a rate of about 500 Hz. Genova, 22 October 2008

  20. Board Carriers OK FEC Carrier FEC Carrier U2F Need a new RCU Carrier Carrier Genova, 22 October 2008

  21. Backplane and Crate • New RCU cables connection. • impedance line, based on ALICE • and PHOS backplane. Need new ALTRO Data And Control backplane May be OK, to be checked. Low Voltages backplane. Voltages needed: RCU, FEC: +4.3V and +3.3V Tx/Rx : +3.3V and -3.3V Need new chassis VME 6U style. Genova, 22 October 2008

  22. NEW ALICE RCU - TOP 23 cm SIU CARD DCS CARD 13.5 cm RCU CARD TOP SIDE Genova, 22 October 2008

  23. New ALICE RCU - BOTTOM BOTTOM SIDE BUS TRANSCEIVERS • FPGA MAIN FUNCTION • Power-On Procedure • FEE Initialization • Dataflow Control • FEE Safety Control RCU to FECs CONNECTORS FPGA XILINX Virtex-II Pro • Reconfiguration Support Elements • FLASH MEM • ProASIC plus Genova, 22 October 2008

  24. Optical link - D-RORC JTAG interface Conf. Flash • FPGA programming anddebugging • Flash memory programming Electrical transceivers • Multi-rate transceivers • Serial-Parallel-Serial converters • Integrated 8B/10B endec • Clock recovery CMC interface • Standard extension I/F • About 180 user I/O Optical transceivers • 850 nm VCSEL laser • 2.125 Gbit/s • Pluggable modules Altera FPGA LVDS interface PCI 64-bit/100 MHz • APEX-E device family • EP20K400E • High-speed serial I/F • 2 inputs + 2 outputs • Purpose: detector busy • +3.3V compatible signals • Bus master enabled Genova, 22 October 2008

  25. D-RORC architecture DIU or Media I/F • PCI interface core • Handles PCI transactions • Performs PCI mastering • Receiver and Transmitter • Buffer data and initiate the DMA • Control registers • Mapped to PCI memory • Provide control interface • Provide status information • DDL interface • Performs DDL transactions • Provides DDL status DIU I/F or DIU core TAF address length Controlregisters TransmitDMA RX FIFO TX FIFO address length ReceiveDMA RAF Slave I/F DMA control Master I/F PCI core(64-bit master, memory mapped) PCI bus TAF – Transmit Address FIFO RAF – Receive Address FIFO Genova, 22 October 2008

  26. Receiver DMA Push Buffer Descriptor #5 Buffer Descriptor #4 Buffer Descriptor #3 Buffer Descriptor #2 Software Buffer Descriptor #1 Receive Address FIFO Firmware Receive Report FIFO Receiver DMA controller DMA report #5 DMA report #4 DDL DMA report #3 DMA report #2 DMA report #1 PC memory, managed by PHYSMEM PCI bus D-RORC Genova, 22 October 2008

  27. Performance: D-RORC Dual Channel • Bandwidth vs. block size measurements with internal and external (DDL) data source using two D-RORC channel • Steady increase until the maximum bandwidth is reached • Internal: BWmax = Fpci [MHz] x 4 [Bytes] x 2 – Loss = 484 MB/s • External: BWmax = BWddl x 2 = 412 MB/s Fpci = 66MHz Genova, 22 October 2008

  28. Software Application (e.g. DATE) D-RORC API layer D-RORC driver Physmem Linux kernel • D-RORC driver: Linux device driver, runtime loadable module • Finds the D-RORC cards on the PCI buses • Maps the registers into the user memory space • D-RORC API layer: collection of library routines written in C • Ensures exclusive access to the hardware using device locking • Provides simple programming I/F for higher level applications • Command line executables • Hardware identification • Reset components (DIU, SIU etc.) • Send commands, reads status • Send data blocks • Receives and checks data blocks Genova, 22 October 2008

  29. Low Voltage Power Supply DELTA ELETTRONIKA • Switching with linear post-regulator • Low noise and ripple 8mVpp • Voltage Remote sensing max 2V • Need Remote Control ?? (option RS232, also Ethernet available but expensive) Double rack mountable Rear view Single Genova, 22 October 2008

  30. Material procurement • 3 RCUs ordered • Agreement with Luciano Musa also for DCS mezzanine without TTCrx • RCUs already delivered to CERN, need debugging • Available 2nd week of November. • Complete optical link available • 3 Serial Interface Units • 2 D-RORCs with DIUs embedded • Fibers • Software available excepted ALICE DATE application and DCS. • Need 100MHz PCI computer with SLC4 32 bit Linux kernel 2.6 • VME chassis ordered, available next week. • Procured sample of ALTRO data and control backplane • Sample of a RCU cable pair extension • Three samples NIM mezzanine for external trigger. • Thanks to HANS MULLER from PHOS detector. • Procured sample of DCS mezzanine • Thanks to Dirk Gottschalk • Need to order Low Voltages Power Supply. • Factory DELTA ELEKTRONIKA Genova, 22 October 2008

  31. To be done • VME crate to be assembled, also minor modification • Readout Backplane • Schematic ready • Layout in progress, need to be finalized following the VME crate constraints • Available end November • Low Voltages Backplane • To be checked. • RCU Carrier, to be done. • Also may be available end November (easy board). • Software installation • DATE • DCS Genova, 22 October 2008

  32. Thank you ! Genova, 22 October 2008

More Related