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Recursively Partitioned Static IP Router Tables

Recursively Partitioned Static IP Router Tables. Author: Wencheng Lu , Sartaj Sahni Publisher: IEEE TC,2010 Presenter: Jia -Wei Yo Date: 2011/09/14. Introduction.

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Recursively Partitioned Static IP Router Tables

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  1. Recursively Partitioned Static IP Router Tables Author: WenchengLu ,SartajSahni Publisher: IEEE TC,2010 Presenter: Jia-Wei Yo Date: 2011/09/14

  2. Introduction • Propose a method to partition a large static router table into smaller tables using a structure, such as a multibittrie (MBT) or a hybrid shape shifting trie (HSST) . • Reduce • Total memory requirement • Worst case number of memory accesses

  3. Recursive Partitioning • (R) : the level descendent of the root R of T. • ST(N):subtrie , rooted at a node N , N (R). ( 0 < s ≤ T.height + 1 ) • L(R) : called the auxiliary partition, defined by prefixes whose length is < s. • Q(N) : the path from the root R to the root N

  4. Incorporating Leaf Pushing • The worst-case number of memory accesses required for a lookup maybe reduced using controlled leaf pushing • Assuming that the original prefix set contains the default prefix, the stated inheritance ensures that every search in a partition finds a matching prefix and hence a next hop.

  5. Optimization • B(N, , r) : be the minimum memory required to represent levels 0 through of the subtree of T rooted at N by a base structure such as MBT or HSST; • H(N ,) : be the memory required for a stride hash table for the paths from node N of T to nodes in (N) • C(N,,r) : be the minimum memory required by a recursively partitioned representation of the subtrie defined by levels 0 through of ST(N).

  6. auxiliary partitions are restricted to be represented by base structures auxiliary structure for prefixes whose length is less than the stride or a simple array with entries when the partition stride is

  7. Implementation For benchmarking purposes, we assumed that the router table will reside on a QDRII SRAM (dual burst), which supports the retrieval of 72 bits of data with a single memory access. We considered two hash table designs—36 and 72 bits.

  8. Experimental Result

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