Overview of OCAPI: Designing FIR Filters and LFSR Using C++
This document provides an introduction to the OCAPI framework used in the design of digital systems, focusing on the complete design flow of Finite Impulse Response (FIR) filter implementation. It contrasts OCAPI with the ART Designer and explores its classes and design cycles. Key topics include fixed-point and floating-point descriptions, the design of Linear Feedback Shift Registers (LFSR), and the process of generating VHDL code from OCAPI models. Practical case studies and homework assignments are also discussed to reinforce learning.
Overview of OCAPI: Designing FIR Filters and LFSR Using C++
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Presentation Transcript
EE213A Spring 2000 Prof. Ingrid Verbauwhede OCAPI http://www.imec.be/ocpai/ Maged Attia(mattia@ucla.edu)
Agenda • Introduction to OCAPI • Case Study: Complete Design Flow of FIR • Homework: Design of LFSR (Wednesday) (Friday) (Friday)
Introduction to OCAPI • OCAPI vs. ART Designer • How does OCAPI work? • OCAPI Classes • Design Cycle in OCAPI • Compiling C++/OCAPI • Introduction to the case study. Outline
csh> g++ file.cxx … csh> OCAPI vs. ART Designer OCAPI Art Designer 1) C++ based 1) C/C++ based 2) Bit Parallel 2) Bit Parallel Arch. 3) 3) 4) More flexible 4) More friendly
VHDL How does OCAPI Work? qlib.h include C++ OCAPI Description Classes libqlib.a Link Add C++ Compiler Mult Ram Sub Run
OCAPI Classes: 1- Fixed Point dfix a; dfix a(0.25); dfix a(0.25, 10 ,8); dfix a(0.25, 10, 8, tc, st, rd); tc: two’s complement ns: unsigned wp: for wrap-around st: saturation fl: for truncation rd: rounding Default
OCAPI Classes: 2- IN/OUT I O a b in.dat queue TX queue out.dat dfix a; FB I(“I”); src a(“a”, I, “in.dat”); dfix b; FB O(“O”); snk b(“b”, O, “out.dat”);
OCAPI Classes: 3- Internal Signal _sig a(“a”); plain signal with fl-p inside it _sig b(“b”, dfix(0, 10, 8) plain signal with fx-p inside it _sig k(0.5); Clk ck; Registered signal C with initial _sig c(“c”, ck , k); value k
OCAPI Classes: 4- FSM ctlfsm f; Creat FSM F << “my_fsm” Give it a name State rst; State active; Rst << “my_rst”; Active << “my_active” F << deflt(rst); Tell which one is the default Active << allways << active; Active << _cnd(a) << rst Creat 2 states Give them name Transitions
Design Cycle in OCAPI • Un-Timed Design • - Easy and fast to design • - Non implementable • - Real description • Timed Design • - Implementable Timed Timed Un-Timed TX RX Channel
C++ C++/OCAPI Floating Foating/DF C++/OCAPI Fixed/DF Design cycle in OCAPI 1) Un-timed Design Refine Non implementable Fixed point EASY Description !!!!!! Function Description Refine Word-length
C++ Floating Design cycle in OCAPI Void add::add( int & in1 int & in2 int & out ) { out = in1 + in2 return 0; } Void main() { Add Add(a, b, c); }
C++/OCAPI Foating/DF Design cycle in OCAPI Void add::add( dfix & in1 dfix & in2 dfix & out ) { if ( ( in1.getsize() <1) || (…..) ) { return 0;} out = in1.get() + in2.get() return 1; } Refine Void main () { FB a(“a); ……………. Src src1(“src1”, a, “src1”) …….. systgen S1(“S1”); S1 << src1; S1 << src2; S1.next << Add; ……….. Void main() { Add Add(a, b, c); }
C++/OCAPI Fixed/DF Design cycle in OCAPI Everything is the same but: instead of: dfix Use: dfix ( , w, l, …)
C++/OCAPI C++ Foating/FSM Floating VHDL Design cycle in OCAPI 2) Timed Design Refine Function Description C++/OCAPI Refine Fixed/FSM Word-length Auto
Design cycle in OCAPI FSM and FG Void add::add( dfix & _in1 dfix & _in2 dfix & _out ) { ctrlfsm _fsm; Sfg _add; State _go; _fsm << deflt(_go) _go << allways<< _add<<_go } Void main () { FB a(“a”); ……………. Src src1(“src1”, a, “src1”) …….. systgen S1(“S1”); S1 << src1; S1 << src2; S1.next << Add; ……….. Clk ck; Int I; For (I=0; I<3; I++) S1.run(clk)
Compiling C++/OCAPI C++/OCAPI VHDL C++
Introduction to the case study Step 1: Specifications -> Coefficients Step 2: Create floating point description for the whole system. Step 3: Create fixed point description for the UPS and the FIR and refine for best word length Step 4: Use that WL to create fx-p FSM description and run timed simulation to generate the VHDL code.
