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Canonical TED Complexity for Software Verification & High-Level Synthesis

Explore the intricacies of Taylor Expansion Diagrams (TED) for software verification and high-level synthesis in computing, discussing their applications, features, and relevance to current industry trends. Dive into the transformative potential of canonical representation for algorithm equivalence checks and streamline high-level synthesis processes with TED. Decode the complexities of Taylor Expansion Diagrams and their role in algorithmic verification, aiming to prove equivalence and optimize designs for enhanced performance. Unravel the power of TED in behavioral synthesis, demonstrating its significance in deriving multiple implementations while maintaining a canonical structure. Discover the future-ready solutions offered by TED in addressing complexities in software verification and high-level synthesis.

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Canonical TED Complexity for Software Verification & High-Level Synthesis

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  1. ECE 665 - Project Ideas Test complexity of TED operationsUse canonical property of TED for- Software Verification- Algorithm Equivalence check- High Level Synthesis Maciej Ciesielski ECE Department University of Massachusetts, Amherst

  2. F(x) x … F(0) F’(0) F’’(0)/2 Taylor Expansion Diagram (TED) • Compact, canonical representation for arithmetic functions (F: Int  Int ) • Treat discrete function as continuous (polynomial) • Taylor Expansion (around x=0): F(x) = F(0) + x F’(0) + ½ x2 F’’(0) + … • Notation F(x=0) 0-child- - - - -- F’(x=0) 1-child---------- ½ F’’(x=0) 2-child====== etc. F(x) = 0-child+ x (1-child) + x2(2-child) + …

  3. X2 = (8x3 + 4x2 + 2x1 + x0)2 (A+B)(A+2C) 64 x3 A 1 16 1 16 x2 x2 B B 8 1 4 C 4 x1 x1 2 4 1 2 1 x0 x0 1 0 1 1 1 1 0 TED – a few Examples A,B,C: arbitrary word width X decomposed in bits TED: not a BDD, not a *BMD, not a decision diagram

  4. TED: Composition & Manipulation • Analogous to BDD and *BMD, TED: • Requires an ordering of variables • Has to be reduced • Has to be normalized • Reduced ordered normalized TED is canonical • Composition of TED: • f = g + h; APPLY(+, g, h) • f = g * h; APPLY(*, g, h) • f = g – h; APPLY(+, g, APPLY(*, -1, h))

  5. A0 A1 FFT(A) A2 FAB1 IFFT0 A3 IFFT1 FAB2 InvFFT(FAB) IFFT2 FAB2 B0 IFFT3 FAB3 B1 FFT(B)  B2 B3  x x x x C0 A[0:3] C1 Conv(A,B) C2 B[0:3] C3 Verification of Algorithmic Specifications Use TED to prove equivalence: IFFTi=Ci

  6. A0 A2 A1 A3 B0 • B2 B3 B1 4 0 Isomorphic TEDs: IFFT(i) Conv(i) IFFT0 = C0 = 4{ A0*B0 + A1*B3 + A2*B2 + A3*B1}

  7. TED for High Level Synthesis • Trends and problems in industry • Design Flow • High level synthesis • Prior art • Problems with prior art • New canonical method • TED’s

  8. Need for abstraction • International Technology Roadmap for Semiconductors (ITRS 2001) Report highlights • Moore’s law will be valid for 10 more years • 10 billion transistors • 10 Ghz • 30nm technology • Enormous complexity can only handled by targeting at high levels of design

  9. Design Flow HDL Behavioral High-level Synthesis RTL Description Pre-Layout Simulation Structural Logic Synthesis Design Iteration Floorplanning Post-Layout Simulation Placement Physical Circuit Extraction Routing Tape-out

  10. Specification (HDL) Area Power Latency Objectives, constraints: ... Data Flow Graph Architectural solution minimized for given objective, constraints Architecture High Level Synthesis

  11. A B A C A C Cycle 1 x + x x x + A B Cycle 1 Cycle 2 Cycle 2 Cycle 3 F F Architecture 1: 2 Mult, 1 Add, L = 2 cycles Architecture 2: 1 Mult, 1 Add, L = 3 cycles High Level Synthesis Example Inputs: A, B, C, D Output: F ……… assign F = A*B + A*C ………. Common Data Flow Graph (DFG)

  12. B C + x Cycle 1 A Cycle 2 F Alternative architecture: 1 Mult, 1 Add, L = 2 cycles Alternative solution • To derive alternative solutions, need new Data Flow Graph • user must rewrite the initial specification (HDL) • replace (A B + A C) by A (B + C) • The data flows are derived directly from user’s specification • There is a need for a higher level of synthesis: • Transformation A*B + A*C = A*(B+C) • Abstract level synthesis should provide • Canonical representation • Basis for optimal solutions for different objectives

  13. x + x x + x x x + High Level Synthesis F = A*B + A*C Specification • Algorithms • Scheduling • Allocation • Resource binding Data flow graph Latency Area A C A B A C Cycle 1 Cycle 1 A B Cycle 2 Cycle 2 Cycle 3

  14. Current HL Transformation Methods • Ad-hoc methods (algebraic) • Commutativity: A + B = B + A • Associativity: A + (B +C) = (A + B) + C • Distributivity: A * (B +C) = (A * B) + (A * C) • Term rewriting, etc. • Tools • Matlab, Maple • Mathematica • Problems: • not canonical • cannot scale with design size • require manual intervention

  15. Taylor Expansion Diagrams • Features of TED • Canonical, minimal, normalized • Compact (linear for polynomials) • Represents word-level blocks and Boolean logic • Applications • Equivalence checking, RTL verification • Symbolic simulation (representation) • Algorithm verification NEW: Application to Behavioral Synthesis

  16. HLD AB + AC A A B C A B C B +   C  + 0 1 F2 = A (B + C) F1 = AB + AC Application to Behavioral Synthesis • Given an algorithm, derive several implementations using common (canonical) structure of TED

  17. + x + x B C Cycle 1 A Cycle 2 Alternative Architecture F = A*(B+C) Specification Data flow graph Area

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