VLSI Design Lecture 1: Digital Systems and VLSI

1. VLSI DesignLecture 1: Digital Systems and VLSI Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Wayne Wolf’s lecture notes

2. Overview • Why VLSI? • Moore’s Law. • The VLSI design process. • IP-based design.

3. Features of Better Circuit • Lower cost (chip area, number of ICs, …) • Better performance (speed) • Lower power • Better reliability • More integration  less inter-chip connections  better reliability • Better testability • Better repeatability • Less design and fabrication time

4. Components of an Electronic System • Chip (usually a small part of the total cost, but can influence the cost of other parts) • Power supply • Fan • PCB (Printed Circuit Board) • Bus • Box

5. Why VLSI? • Integration improves the design: • lower parasitic = higher speed; • Shorter length of signal transfer is another reason for higher speed (3 cm wire  3*10-2/3*108 = 0.1nsec) • lower power (hence better reliability); • Power is a limiting factor for high integration. • physically smaller. • Integration reduces manufacturing cost-(almost) no manual assembly. • Greatly reduces cost of parts other than chip (supply, fan, PCB, …) • ASIC might be more expensive than standard IC, but system’s cost will be lower.

6. Levels of Integration • SSI  MSI  LSI  VLSI • Criteria: • Gate count (2-20, 20-200, 200-2000, 2000 +); you may see different numbers in literature • Pin count • Feature size (line widths, line spacing, size) • Chip size • Function (gate & FF, module, subsystem, system)

7. Levels of Integration (cont’d) • Where to go after VLSI? • ULSI (Ultra Large Scale Integration - which is between 500,000 and 10,000,000 transistors), • GSI (Gigantic Scale Integration - which is over 10,000,000 transistors). • Who knows the next step? Maybe: • UBSI (Unbelievably Big Scale Integration)! or • YWBHLI (You Wouldn't Believe How Large the Integration is)!!

8. VLSI and you • Microprocessors: • personal computers; • microcontrollers. • DRAM/SRAM. • Special-purpose processors.

9. log(#dev) t Moore’s Law • Gordon Moore(co-founder of Intel( predicted that number of transistors per chip would grow exponentially (doubles every 18 months). • Exponential improvement in technology is a natural trend: steam engines, automobiles. • Obstacles for Moore’s law: • Quantity and variety of products which use ICs has had less progress. • Cost of design verification and test is large. • Complexity of design makes it difficult to manage it among design and engineering groups. • Role of CAD tools.

10. Moore’s Law plot

11. Moore’s Law and Intel processors

12. Moore/Intel log scale

13. Transistors/Intel Microprocessors

14. Terminology • Manufacturing node: technology at a particular channel length. • Deep submicron technology: 250-100 nm. • Nanometer technology: 100 nm and below.

15. The cost of fabrication • Current cost: $4 billion. • Typical fab line occupies about 1 city block, employs a few hundred people. • Most profitable period is first 18 months-2 years.

16. Cost factors in ICs • For large-volume ICs: • packaging is largest cost; • testing is second-largest cost. • For low-volume ICs, design costs may swamp all manufacturing costs. • IC manufacturing technology is remarkably versatile (change masks). • Wafer size: 12 inch (moving to 18 inch) • Chip size: 1.5 X 1.5 cm2 (moving to 2 X 2)

17. Cost of design • Design cost can be significant: $20 million for a large ASIC, $500 million for a large CPU. • Cost elements: • Architects, logic designers, etc. • CAD tools. • Computers the CAD tools run on.

18. Intellectual property • Intellectual property (IP): pre-designed components. • May come from outside vendors, internal sources. • IP saves time, design cost. • IP blocks must be designed to be reused.

19. Reliability • Nanometer technologies require attention to reliability. • Design-for-manufacturing (DFM) and design-for-yield (DFY) techniques adjust the design to improve yield. • Circuit and architecture techniques can compensate for unreliable components.

20. The VLSI design process • May be part of larger product design. • Major levels of abstraction: • specification; • architecture; • logic design; • circuit design; • layout.

21. Role of Each Level • Specification: function, cost, etc. • Architecture: large blocks. • Logic: gates + registers. • Circuits: transistor sizes for speed, power. • Layout: • Layout size determines fabrication cost. • Shapes determine parasitics; hence the circuit speed and power.

22. Challenges in VLSI design • Multiple levels of abstraction: transistors to CPUs. • Multiple and conflicting constraints: low cost and high performance are often at odds. • Short design time: Late products are often irrelevant. • 6 months delay  losing 33% of the profit

23. Techniques to eliminate unnecessary detail • Hierarchical design (divide and conquer, i.e.; breaking the chip into a hierarchy of components, where each consists of a body and a number of pins) • Design abstraction (use multiple levels of abstraction) • Using CAD tools: tries to solve all 3 mentioned problems; • dealing with multiple levels of abstraction is easier when you are not absorbed in the details, • computer programs can analyze cost trade-offs much better (because they are methodical) • computers are much faster than humans.

24. CAD Tools Categories • Design entry tools (e.g., schematic capture) • capture a design in machine-readable form for use by other programs, but don’t do any real design work. • Analysis and verification tools (e.g., spice) • ease the analysis task, but don’t tell how to change the circuit for the desired function/spec. • Synthesis tools (e.g., Leonardo) • create a design at a lower level of abstraction from a higher level description. • Both hierarchical design and design abstraction are as important to CAD tools as they are to humans.

25. Dealing with complexity • Divide-and-conquer: limit the number of components you deal with at any one time. • Group several components into larger components: • transistors form gates; • gates form functional units; • functional units form processing elements; • etc.

26. Hierarchical name • Interior view of a component: • components and wires that make it up. • Exterior view of a component = type: • body; • pins. cout Full adder sum a b cin

27. Add2.a Add1.a Instantiating component types • Each instance has its own name: • add1 (type full adder) • add2 (type full adder). • Each instance is a separate copy of the type: cout Add2(Full adder) Add1(Full adder) sum sum a a b b cin cin

28. A hierarchical logic design box1 box2 x z

29. Net list: net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet Net lists and component lists

30. Component hierarchy top i1 xxx i2

31. Hierarchical names • Typical hierarchical name: • top/i1.foo pin component

32. English Throughput, design time Executable program Function units, clock cycles function Sequential machines cost Literals, logic depth Logic gates nanoseconds transistors microns rectangles Design abstractions specification behavior register- transfer logic circuit layout

33. Layout and its abstractions Layout for dynamic latch:

34. Stick diagram

35. Transistor schematic

36. Mixed schematic inverter

37. Circuit abstraction Continuous voltages and time:

38. Digital abstraction Discrete levels, discrete time:

39. Register-transfer abstraction Abstract components, abstract data types: 0010 + 0001 + 0111 0100

40. Top-down vs. bottom-up design • Top-down design adds functional detail. • Create lower levels of abstraction from upper levels. • Bottom-up design creates abstractions from low-level behavior. • Good design needs both top-down and bottom-up efforts.

41. Design validation • Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. • Forward checking: compare results of less- and more-abstract stages. • Back annotation: copy performance numbers to earlier stages.

42. Manufacturing test • Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. • Must quickly check whether manufacturing defects destroy function of chip. • Must also speed-grade.

43. IP-based design • Almost every chip uses some form of IP: • Standard cell libraries. • Memories. • IP blocks. • Designers must know how to: • Create IP. • Use IP.

44. Types of IP • Hard IP: • Pre-designed layout. • Allows more detailed characterization. • Soft IP: • No layout---logic synthesis, etc. • IP layout is created by the IP user.

45. Hard IP • Must conform to many standards: • Layout pin placement. • Layer usage. • Transistor sizing. • Hard IP blocks are usually qualified on a particular process. • Qualification: Component is fabricated and tested to show that the IP works on that fab line.

46. Soft IP • Conformance of layout to local standards is easier since it is created by the user. • Timing can only be estimated until the layout is done. • Must conform to interface standards. • A wrapper adapts a block to a new interface.

47. IP across the design hierarchy • Standard cells. • Pitch matched in rows, compatible drive. • Register-transfer modules. • Memories. • CPUs. • Buses. • I/O devices.

48. Specifying IP • Hard or soft? • Functionality. • Performance, including process corners. • Power consumption. • Special process features required.

49. The I/O lifecycle specification IP creation HDL design database extraction characterization and validation documentation design IP documentation IP database qualification IP use IP modules chip design

50. Using IP • May come from vendor, open source, or internal group. • Must identify candidate IP, evaluate for suitability. • May have to pay for IP. • May want to qualify IP before use, particularly if it pushes analog characteristics.