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JAZiO ™ Incorporated JAZiO

Digital Signal Switching Technology. JAZiO ™ Incorporated www.JAZiO.com. What is JAZiO Technology?. A new method of interchip I/O switching At high data rate with low latency With low power At low cost Effectiveness is due to using Differential sensing with a single pin per bit

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JAZiO ™ Incorporated JAZiO

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  1. Digital Signal Switching Technology JAZiO™ Incorporated www.JAZiO.com

  2. What is JAZiO Technology? • A new method of interchip I/O switching • At high data rate with low latency • With low power • At low cost • Effectiveness is due to using • Differential sensing with a single pin per bit • Built in timing • Look for change-of-data first • Transition detection

  3. Next bit time One bit time tRF tSU tHD Sharp Edges Cause: All information is transmitted during tRF (1/3 of bit time) Ground Bounce! Cross Talk! Ringing! EMI! High Power! The rest of the bit time is just wasted! Traditional Signal Driving(Peak Detection)

  4. Next bit time One bit time VREF  0.8V Sensing Level Switching Level Large switching levels cause: Sensing level about 1/3 of switching level Ground Bounce! Cross Talk! Ringing! High Power! The rest of the switching level is just wasted! Pseudo Differential Signal Sensing

  5. JAZiO Solution • JAZiO has invented a system which • Achieves very high performance • Has edges which can take the whole bit time • Detects data value as soon as transition occurs • Uses differential sensing with low signal levels • Yet has only 1 pin per data signal

  6. What’s the Secret? A Re-think • For each data signal, there is either a change or no-change from the previous bit time • Traditional systems are good on no-change but bad on change • JAZiO looks for change first and then adjusts if no-change occurs • For JAZiO the decision binary is change or no-change rather than high or low voltage

  7. VTR Provide alternating Voltage/Timing References switching at the data rate VTR 3 7 Data is driven coincidentally with Voltage/Timing References Data Input 1 5 2 6 8 4 8 different combinations of VTR and Data Input One Bit Time Next Bit Time A Dual Comparators are used VTR Data Input Data Output Steering Logic B VTR JAZiO Solution In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change

  8. Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

  9. VTR Data Input VTR Steering Logic A out in XOR • Generate Steering Logic signals (SL and SL) • Use them with Data Output from previous Bit Time to select between Comparators A and B • Also use them for data latching in Receiver Output B in out in XOR VTR SL Latching System Latched Output VTR SL VTR

  10. Data Input Data Input VTR XOR SL Initialization or Receiver Enable Data Output SL XOR VTR 55 Small Transistors Per Bit No PLL/DLL Required No die size penalty!!!

  11. The receiver cell is: 22um x 55um (Including routing channels) The pad cell is: 70um x 80um

  12. A out in VTR XOR in Data Output Data Input B in out in VTR XOR VTR SL Determine no-change and switch to Comparator B VTR SL VTR First Look for change Data Input  0.5V VTR Time Domain Decision is made in the Time Domain rather voltage domain

  13. JAZiO™ Receiver Operation A out in XOR-A in Data Output B VTR in out in XOR-B Data Input The No-change Cases VTR SL VTR VTR SL VTR Initialize 0 1 1 0 0 1 Data Input VTR VTR SL CompA SL XOR-A CompB XOR-B Data Output

  14. This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.). THE GAP THE GAP BECOMES INFINITE 3 Data In Comp A Data In 1 1 VTR 1 VTR No Change Change Change • Case 3: Comp A remains High past the point of change and the Data Output retains the previous data • The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output Change /No Change Concept Comp A THE GAP • Case 1: Comp A amplifies the change and the data passes through the Steering Logic

  15. A VTR out in SL XOR-A Data Output in Data Input (High) B in VTR out in SL XOR-B Bit Time But! The handoff from Comparator A to B is smooth since both comparators and Data Output are all high After the handoff, Comparator B is ready to make the next differential comparison Since Comparator A is selected its high value causes Data Output to remain high The No-Change Case Comparator A is selected and as the differential on its inputs disappears the output remains high temporarily However, Comparator B is gaining a differential and its Output becomes a solid high But eventually the SLs will switch causing the XORs to switch and Comparator B will be selected

  16. Break-Before-Make (Break-And-Remake) 1.8 Xnorb xnora vtr 1 Data Input Voltage (V) Data Output 0 4 5 6 4nH Package Time (nS)

  17.  500mV Data Skew at Receiver Data Input 1.25V/ns + 100mV - 150mV Recommended Skew band VTR Bit time = 0.5ns Simulations show that width of Skew Band can be up to 40% of bit time

  18. data_out 0 data_out 1 data_out2 data_out 3 sl slb xora xorb xora xorb xorb xorb xora xora vtr vtrb SIGNALS FROM PADS data_in0 data_in1 data_in3 data_in2 4 Bit JAZiO Receiver From Test Chip

  19. Latch (latching at ¼ the data rate) 4 of 16Serial to Parallel 4 of 16Serial to Parallel 4 of 16Serial to Parallel 4 of 16Serial to Parallel 4-bitJAZiOReceiver 4-bitJAZiOReceiver 4-bitJAZiOReceiver 4-bitJAZiOReceiver vtrb data_in0 data_in1 data_in2 data_in3 data_in4 data_in5 data_in6 data_in7 vtr data_in8 data_in9 data_in10 data_in11 data_in12 data_in13 data_in14 data_in15 16 JAZiO™Receivers From Test Chip

  20. Transition Detection Higher frequency components, above the maximum operating frequency, can be filtered out at the receiver. Narrower voltage band for differential amplifier operation (£300mV). Self aligned data and VTRs shifts the steering logic time, latching window and change/no-change gap in real time relative to Vcc, temperature, manufacturing variations. VH 600mV Diff Amp Band Vref Band 300mV Diff Amp Band VL Transition Detection • Pseudo Differential Peak Detection • Frequency components higher than the maximum frequency need to be present at the receiver (setup and hold time at VOH/VOL). • Wider voltage band for differential amplifier operation is required (³600mV). • Vref is a voltage average (Vcc, temperature and manufacturing, and noise). • Clock is a time average based on PLL/DLL.

  21. Low Pass Filter P-Ch Clamp To Receiver 1nH 1nH 0.2 200 0.24 Pad Cint 1pf 0.6pf 0.6pf 0.1pf 0.1pf Lead frame Bond Wire N-Ch Clamp Input Protection Resistor 2nH Package & ESD Model

  22. 1.8 Data Output Data Input 1 Voltage (V) At Pin VTR 0 5 6 7 8 9 Time (nS) 1.8 At Receiver Input Data Output Data Input 1 Voltage (V) VTR 0 5 6 7 8 9 Time (nS) Simulation at 2Gb/s Middle of transmission line Package inductance 2nH

  23. 10G • Slower edges • Lower switching levels • Reduced slew rate JAZiO™ Better JAZiO™ 1G JAZiO™ RDRAM Data Rate per Pin (b/S) DDR SDRAM-100 100M SDRAM-66 EDO-33 10M 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Slew Rate (V/nS) Data Rate vs Slew Rate Comparison Higher Performance at Lower Power with Higher Robustness

  24. JAZiO Is Entirely Common-Mode Common Mode VTT Common Mode VTT JAZiO Signal VTR Common Mode Noise Sources VTT Common Mode VTT Signal Pseudo Differential VREF Noise Sources Noise Sources • VSSQ noise between signal and VREF • VTT noise and/or VTT mismatch on either end • VREF impedance to Signal impedance mismatch

  25. Applying JAZiO Technology • JAZiO is the physical I/O layer only • JAZiO provides no protocol • Works with any protocol • Like steel belted radial tires that work for Honda Civic, Ferrari Sports Car, or Ford Explorer • Easy to use • No die size penalty • No PLL/DLL or special semiconductor technology • Low Power • Can be used anywhere that fast switching or low power is useful

  26. JAZiO for DRAM • JAZiO Technology can be applied to scaled-up versions of existing protocols like DDR or RDRAM • Or new protocols can be developed to match JAZiO’s low latency and high bandwidth to reduce pins and increase parallelism

  27. 1GHz CPU L3 L3 L3 L3 BSB All scalable to 2x frequencies CPU CPU CPU CPU FSB CONTROLLER DRAM 2GHz Data Rate Quad Processor Module Quad Processor Module I/O 2GHz Interprocessor Communication (Scalable to 4GHz) Quad Processor Module Quad Processor Module 16-Wide MP Server with 2GHz FSB & BSB

  28. JAZiO™ SOC DRAM Power consumed in the memory interface is reduced due to low switching levels of VTT=1.0v and VLOW=0.5v Pavg = K•Dv•VTT K a (Cf+1/Rt) Therefore Power Ratio = (0.5v•1)/(0.8v•1.8) » 1/3 When compared to existing pseudo differential with VTT=1.8v, VLOW=1.0v, similar load capacitance, operating frequency and termination resistance Notebook / Internet Appliance Small swing and slower transition time reduces EMI allowing it to meet FCC limits for radiation

  29. How Can JAZiO Be Used? • JAZiO is “essentially” an Open Standard • All technology is publicly visible w/o NDA • Anyone can see it, study it, simulate it, design it in, build test chips, build prototypes, etc • Just don’t sell products without licensing it • A JAZiO demonstration chip has been designed by Micro Magic, Inc – a JAZiO Design Services partner (www.micromagic.com)

  30. Conclusion • JAZiO uses lower levels and slower edges • Achieves high performance, low power, high robustness • JAZiO technology is fundamentally different from traditional methods • Transition Detection rather thanPeak Detection • Time domain rather than voltage domain • Look for changefirst • Change vs No-change rather than High or Low • JAZiO is available to everyone at low cost and applies to any application

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