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Recent modification to TTM/DOCK operation

Recent modification to TTM/DOCK operation. Bit inversion on TTM RAM Test TTM Implement RAM monitor Save DOCK power consumption Disable TA lower mbias Abnormal current Investigation and solution. TTM RAM bit inversion. Bit inversion on TTM (S6 and S7) Strip has been shifted in readout

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Recent modification to TTM/DOCK operation

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  1. Recent modification to TTM/DOCK operation • Bit inversion on TTM RAM • Test TTM • Implement RAM monitor • Save DOCK power consumption • Disable TA • lower mbias • Abnormal current • Investigation and solution

  2. TTM RAM bit inversion • Bit inversion on TTM (S6 and S7) • Strip has been shifted in readout • Bit inversion occurred on hybrid clock • Two TTMs replaced • Exp45 run92～ • Test with 1/10 system • Confirmed that Bit inversion occurred • Slave7 2hours～1 days later • Slave6 2 days～3 days 16bits*64k

  3. Clock defect

  4. Implement parity bit • Modified • ram.dat file (16 bits) • add parity bit • Firmware on TTM • Check bit sum (64MHz) • TTM daemon • Save check sum result to NSM (every 1 minutes) • KD(SVD master control daemon) • Monitor NSM record • If KD found error, send warning to MD

  5. NSMMon on SVD local win@B3 • Monitor implemented on Nov 24 • If bit inversion were detected • Warning ⇒FATAL • Asked to Kusaka • No error has been detected

  6. Save DOCK power consumption • Disable TA • Disable TA with mask bit 　⇒　no change • Loosened the bias of fast shaper • Keep bias of discriminator, filter as high value (need to keep noise low) • A+-, A-- : 5.6A ⇒ 5.1A • Adopt low mbias • 2mA/hyb(VA typ.)⇒1.6mA/hyb • Use fast Tp setting to keep hold timing • A+-, A-- : 5.1A ⇒ 4.1A • Nov 11, Exp47 run52～ • Noise increase on some hybrids: S/N degraded

  7. Hybrid 0 Noise (ADC) Signal (ADC) S/N 100 400 [run]

  8. Abnormal large current LVPS current • B4 LV connector temperature is monitored after repair of LV cable • Temp. exceeded limit • Then we found LV current become large at the beginning of run after VA off • I confirmed that VA is turned on and then initialized correctly. B4 conn. Temp.

  9. Nov 23 morning Run303 start Run303 start VA init VA init LV current is kept large until readout sequence start

  10. Dreset • Dreset ⇒set shift register in VA to the first channel • Power-on state of VA • Shift register position is unknown • Level of output buffer is also unknown Analog driver on REBO take larger current to drive abnormal voltage level Add “dreset” at the end of initialize sequence of VA

  11. Driver on REBO & VA LV current on F0 [A] Short Driver on REBO We need dreset when VA is turned on!!

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