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Hardware Design

Hardware Design. Objectives. After completing this module, you will be able to: List the functionality that defines an arbiter, a master, and a slave List various buses available in MicroBlaze  and PowerPC  processors Discuss the six configurations of the MicroBlaze processor

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Hardware Design

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  1. Hardware Design

  2. Objectives After completing this module, you will be able to: • List the functionality that defines an arbiter, a master, and a slave • List various buses available in MicroBlaze and PowerPC processors • Discuss the six configurations of the MicroBlaze processor • Discuss the JTAG interface in Virtex-II Pro devices

  3. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  4. Buses 101 • A bus is a multi-wire path on which related information is delivered • Address, data, and control buses • Processor and peripherals communicate through buses • Peripherals may be classified as • Arbiter, master, slave, or master/slave (bridge) Arbiter Arbiter Master Master/ Slave Master Slave Slave Slave

  5. Buses 101 • Bus masters have the ability to initiate a bus transaction • Bus slaves can only respond to a request • Bus arbitration is a three-step process: • A device requesting to become a bus master asserts a bus request signal • The arbiter continuously monitors the request and outputs an individual grant signal to each master, according to the master’s priority scheme and the state of the other master requests at that time • The requesting device samples its grant signal until the master is granted access. The master then initiates a data transfer between the master and a slave when the current bus master releases the bus • Arbitration mechanisms • Fixed priority, round-robin, a hybrid

  6. PowerPC Bus Example PLB Bus Data- 64 bits Address- 32 bits OPB Bus Data- 32 bits Address- 32 bits DSOCM Bus Data- 32 bits Address- 32 bits IIC DDR BRAM UART SDRAM DSOCM BRAM GPIO DSPLB ISPLB INTC Ethernet OPB2PLB PLB2OPB LCD PPC405 DCR BRAM ISOCM DCR Bus Data- 32 bits Address- 10 bits INTC BRAM ISOCM Bus Data- 64 bits Address- 32 bits PLB ARB OPB ARB

  7. MicroBlaze Bus Example IIC IOPB Bus ILMB Bus UART MicroBlaze GPIO Ext Mem BRAM ILMB IOPB Ethernet DLMB DOPB LCD DLMB Bus DOPB Bus BRAM All buses are 32 bits INTC OPB ARB

  8. CoreConnect • The IBM CoreConnect standard provides three buses for interconnecting cores, library macros, and custom logic: • Processor Local Bus (PLB) • On-chip Peripheral Bus (OPB) • Device Control Register (DCR) bus • IBM offers a no-fee, royalty-free CoreConnect architectural license • Licenses receive the PLB arbiter, OPB arbiter, and PLB/OPB bridge designs along with bus-model toolkits and bus-functional compilers for the PLB, OPB, and DCR buses • Required only if you create your own CoreConnect peripheral or you are using Bus Functional Model (BFM)

  9. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  10. PLB Bus • Connection infrastructure for high-bandwidth master and slave devices • Fully synchronous to one clock • Centralized bus arbitration—PLB arbiter • 64-bit data bus • Addresses high-performance, low-latency, and design-flexibility issues through: • Decoupled address and read and write data buses with split transaction capability • Concurrent read and write transfers yielding a maximum bus utilization of two data transfers per clock • Address pipelining that reduces bus latency by overlapping a new write request with an ongoing write transfer and up to three read requests with an ongoing read transfer • Ability to overlap the bus request and grant protocol with an ongoing transfer

  11. PLB Interconnect / Architecture • One to 16 PLB masters, each connect all of their signals to the PLB arbiter • The PLB arbiter multiplexes signals from masters onto a shared bus to which all the inputs of the slaves are connected • One to n PLB slaves OR together their outputs to drive a shared bus back to the PLB arbiter • The PLB arbiter handles bus arbitration and the movement of data and control signals between masters and slaves

  12. PLB Arbiter • PLB master • Arbitration support for up to 16 masters • The number of PLB masters is configurable via a design parameter • PLB address pipelining • Three-cycle arbitration • Four levels of dynamic master request priority • PLB slave • Supports up to 16 slaves • The number of PLB slaves is configurable via a design parameter • No external OR gates are required for PLB slave input signals • PLB architecture compliant

  13. Arbitration Priority • During the bus arbitration cycle, the bus arbitration control unit uses the M_priority[0:1] signals to determine which master is granted the bus • Only the priority inputs of masters with their respective M_request[n] signal asserted are used in determining the highest request priority • Priority to each device is automatically assigned as the masters are added • Priorities can be changed in the MHS file by using the following syntax • BUS_INTERFACE MOPB = instance_name POSITION = integer • The integer is a positive number, with 1 being for the highest priority

  14. Resolving Priority • The Xilinx PLB implements a fixed-priority scheme to handle “tie” situations, which occur when two or more masters have the same level of request priority

  15. PLB Bridge • The PLB-to-OPB bridge translates PLB transactions into OPB transactions • This bridge functions as a slave on the PLB side and a master on the OPB side • The bridge contains a DCR slave interface to provide access to its bus error status registers • The bridge is necessary in systems where a PLB master device, such as a CPU, requires access to OPB peripherals

  16. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  17. OPB Bus • The OPB bus decouples lower bandwidth devices from the PLB • It is a less complex protocol than PLB • No split transaction or address pipelining capability • Centralized bus arbitration—OPB arbiter • Connection infrastructure for the master and slave peripheral devices • The OPB bus is designed to alleviate system performance bottlenecks by reducing capacitive loading on the PLB • Fully synchronous to one clock • Shared 32-bit address bus, shared 32-bit data bus • Supports single-cycle data transfers between the master and the slaves • Supports multiple masters, determined by arbitration implementation • The bridge function can be the master on the PLB or OPB

  18. OPB Bus • Supports 16 masters and an unlimited number of slaves (limited by the expected performance) • The OPB arbiter receives bus requests from the OPB masters and grants the bus to one of them • Fixed and dynamic (LRU) priorities • Bus logic is implemented with AND-OR logic. Inactive devices drives zeros • Read and write data buses can be separated to reduce loading on the OPB_DBus signal

  19. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  20. DCR Bus • Device-control register bus • IBM CoreConnect standard • Used to talk to control registers (1024 total) • 32-bits-wide dataall cycles word-oriented • Supports read and write only, no burst cycles • Simple acknowledgement termination • CPU supports special privileged instructions for access to the DCR • Normal DCR requires special CPU assembly code to access • There is a “fixed” 1024-word I/O space • Must be privilege mode to access registers • Not easy to use without special C function headers or inline ASM

  21. PPC405 DCR Devices dcr_ABus C405DCRABUS dcr_WrData C405DCRDBUSOUT dcr_RdData DCRC405DBUSIN dcr_Read C405DCRREAD C405DCRWRITE dcr_Write dcr_Clk DCRC405ACK dcr_Ack DCR Bus

  22. Memory Mapped DCR • DCR bridges allow memory mapping of DCR space anywhere within the system memory • OPB DCR bridge • Allows DCR devices to exist within 4 KB of contiguous space • Must be accessed on word boundaries and one word at a time • Easier to use, but it requires a PLB and OPB transaction

  23. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  24. OCM Bus • 405 OCM I/Fs • PPC405 has a separate interface used for high-speed access of on-chip memory • PPC405 presents address on both the PLB bus and the OCM bus • Addresses cannot exist in both PLB and OCM space • OCM addresses are non-cacheable, leaving the cache resources for the PLB accesses • The processor block contains the OCM controllers • The processor block contains dedicated controllers to interface between the OCM I/F and FPGA BRAM • There are separate independent controllers for the I-side and D-side to provide higher performance • All signals are in big-endian format

  25. OCM Bus • Features • Independent 16-MB logical space for each of the DSOCM and ISOCM • 16 MB must be reserved regardless of actual memory used • 64-bit ISOCM and 32-bit DSOCM • Up to 128 KB / 64 KB (ISOCM / DSOCM) using programmable BRAM aspect ratios • Programmable processor versus BRAM clock ratio • DSBRAM load: BRAM initialization (Data2MEM), CPU, and FPGA using dual-port BRAM • ISBRAM load: BRAM initialization (Data2MEM) and DCR • CPU DCR-accessible registers

  26. OCM Bus • Benefits • Avoids loads into cache, reducing pollution and thrashing • Has fast-fixed latency of execution • On the D-side, dual-port BRAM enables a bidirectional data connection with the processor • Sample uses • I-side: Interrupt service routines, boot-code storage • D-side: Scratch-pad memory, bidirectional data transfer

  27. Bus Timing • Use timing constraints to determine which ratio to use • *There are two independent clocks for each OCM controller: • BRAMDSOCMCLK • BRAMISOCMCLK

  28. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  29. LMB Bus • The LMB provides single-cycle access to on-chip dual-port block RAM • LMB provides simple synchronous protocol for efficient block RAM transfers • LMB provides maximum guaranteed performance of 125 MHz in Virtex-II devices for local-memory subsystem • DLMB: Data interface, local memory bus (BRAM only) • ILMB: Instruction interface, local memory bus (BRAM only)

  30. LMB Bus Timing • Rules for generating an LMB clock • The MB, LMB, and OPB clock must be the same clock • Use timing constraints to determine the clock speed

  31. Bus Summary

  32. Bus Summary

  33. Review Questions • What is the advantage of using the memory-mapped DCR component? • What is the disadvantage of using the memory-mapped DCR component? • Which buses are included in the CoreConnect standard? • What is the maximum performance of the LMB in a Virtex-II device?

  34. Answers • What is the advantage of using the memory-mapped DCR component? • Does not require inline ASM instructions to access the bus • What is the disadvantage of using the memory-mapped DCR component? • Requires a PLB and an OPB transaction • Which buses are included in the CoreConnect standard? • PLB, OPB, and DCR • What is the maximum performance of the LMB in a Virtex-II device? • 125 MHz

  35. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  36. MicroBlaze Processor • Embedded soft RISC Processor • 32-bit data • 32-bit instruction word (three operands and two addressing modes) • 32 registers (32-bit wide) • 3 pipe stages (single issue) • Big-endian format • Buses • Full Harvard-architecture • OPB (CoreConnect standard), instruction and data • LMB for connecting to local BRAM (faster), instruction and data

  37. MicroBlaze Processor • ALU • Uses hardware multipliers in Virtex-II architecture • Barrel shifter • Program counter • Instruction decode • 32-bit registers • Instruction cache • Configurable size—2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB • Speeds up a typical program running from 60 nS (16 MHz) external memory by three to six times • Bus interfaces • Instruction and data

  38. MicroBlaze Performance • 150 MHz on Virtex-II Pro (-6) devices • 100 Dhrystone-MIPs using LMB BRAM • All instruction takes one clock cycle, except… • Load and store (two clock cycles) • Multiply (two clock cycles) • Branches (three clock cycles, can be one clock cycle) • Approximately 900 LUTs (450 slices, 110 Virtex-II CLB)

  39. 0xFFFF_FFFF Peripherals OPB Memory LMB Memory 0x0000_0018 Interrupt Address 0x0000_0010 Exception Address 0x0000_0008 Reset Address 0x0000_0000 MicroBlaze Memory Space • Memory and peripherals • The MicroBlaze processor uses 32-bit addresses • Special addresses • MicroBlaze processors must have user-writable memory from 0x00000000 through 0x00000017 • BRAM size limits • The amount of BRAM memory that can be assigned is limited • The largest supported BRAM memory size for Virtex and Virtex-E is 16 kilobytes; for Virtex-II, it is 64 kilobytes

  40. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  41. Bus Configuration Systems

  42. Configuration 1 • Large external instruction memory • Fast internal instruction memory (BRAM) • Large external data memory • Fast internal data memory (BRAM)

  43. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logicin PowerPC • JTAG Configurations in Virtex-II Pro

  44. PowerPC Processor Note: The OCM bus does not connect to the cache controller

  45. PowerPC Processor • A 32-bit implementation of the PowerPC embedded-environment architecture • Support for embedded-systems applications • Flexible memory management • Multiply and accumulate instructions for computationally intensive applications • Enhanced debug capabilities • 64-bit time base • Programmable interval (PIT), fixed interval (FIT), and watchdog timers • Performance-enhancing features • Static branch prediction • Five-stage pipeline • Hardware multiply/divide for faster integer arithmetic • Enhanced string and multiple-word handling • Minimized interrupt latency

  46. 0xFFFF_FFFC Reset Address PLB/OPB Memory 0xFFFF_0000 PLB/OPB Memory Peripherals 0x0000_0000 PowerPC • Memory and peripherals • PPC405 uses 32-bit addresses • Special addresses • Every PowerPC system should have the boot section starting at 0xFFFFFFFC • The default program space occupies a contiguous address space from 0xFFFF0000 to 0xFFFFFFFF • If interrupt handlers are present, .Vectors should start at 64K boundary

  47. Outline • Buses 101: Arbiter, Master, Slave • PLB • OPB • DCR • OCM • LMB • MicroBlaze Processor Programmer’s Model • MicroBlaze Configurations • PowerPC Processor Programmer’s Model • Reset Logic in PowerPC • JTAG Configurations in Virtex-II Pro

  48. Reset Interface

  49. PROC_SYS_RESET • Asynchronous external reset input is synchronized with the clock • Asynchronous auxiliary external reset input is synchronized with the clock • Both the external and auxiliary reset inputs are selectable active-High or active-Low • Selectable minimum pulse width for reset inputs to be recognized • Selectable load equalizing • DCM-locked input • Power-on reset generation • Sequencing of reset signals coming out of reset: • First — Bus structures come out of reset • PLB and OPB arbiter and bridges for example • Second — Peripherals come out of reset 16 clocks later • UART, SPI, and IIC, for example • Third — The CPUs come out of reset 16 clocks after the peripherals

  50. 1 2 3 4 5 6 PROC_SYS_RESET • If C_EXT_RST_WIDTH is set to five and C_EXT_RESET_HIGH is set to zero, then the Ext_Reset_In must become active and stay active for at least five clocks before a reset is initiated

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