1. 16.317: Microprocessor System Design I Instructor: Dr. Michael Geiger Spring 2012 Lecture 25: Interfacing (cont.)

2. Lecture outline • Announcements/reminders • Exam 2: next Wednesday • Once again, allowed 1 8.5” x 11” sheet of notes • I’ll provide you with a list of instructions—will post to the web page shortly • Practice problems to be posted today • Lecture outline • Review: microprocessor interfaces • More on 80386 interfaces Microprocessors I: Lecture 25

3. Review: 80386 Interfaces (Fig 9.3, p. 376) A2-A31 HOLD DMA interface HLDA BE0-BE3 D0-D31 INTR Interrupt interface W/R NMI Memory/ IO interface D/C RESET M/IO ADS PEREQ READY Coprocessor interface BUSY NA ERROR LOCK BS16 Microprocessors I: Lecture 25

4. Additional Memory/IO signals • LOCK: used in multiprocessor systems • One processor must claim bus control to execute transaction • BS16: Change buses to 16-bit mode Microprocessors I: Lecture 25

5. Interrupt Interface • Signals: • INTR: interrupt • NMI: Nonmaskable interrupt request • RESET: system reset • Interrupt request/interrupt-acknowledge signal handshake • IF can disable INTR; NMI cannot be disabled • RESET: initialize internal registers, execute reset service routine Microprocessors I: Lecture 25

6. DMA and Coprocessor Interfaces • DMA • Two signals: HOLD and HLDA • HOLD: bus hold request by DMA controller • 80386DX goes into hold state, its bus signals are in high-impedance state • HLDA: acknowledge from 80386DX to give up control of bus • Coprocessor Interface • PEREQ: coprocessor request for data transfer • BUSY: coprocessor busy; no new calculation • ERROR: coprocessor error occurred Microprocessors I: Lecture 25

7. System clock • Used to synchronize both internal and external operations • Generated by external oscillator • Specified in terms of frequency or cycle time • Cycle time = 1 / frequency • E.g. 20 MHz clock  cycle time = 1 / 20x106= 50 ns • 80386 specifics • External pin CLK2: clock input • Internal clock: ½ frequency of CLK2 • Valid internal frequencies for different 80386 models: 16, 20, 25, 33 MHz • One (internal) cycle: 1 “T state” Microprocessors I: Lecture 25

8. Bus Cycles • Activity performed when accessing information in memory or I/O devices • Nonpipelinedvs pipelined • Nonpipelined bus cycle (Figure 9.10) • T1 : outputs the address on address bus, a bus cycle indication code, control signal • T2: external device accept data, or provide data to data bus • address is still available on address bus while data transfer • Each bus cycle has two T states (= 4 CLK2 cycles = 100ns for 20MHz 80386) Microprocessors I: Lecture 25

9. Pipelined Bus Cycle • Pipelining : Addressing for the next busy cycle is overlapped with data transfer of prior bus cycle (Fig 9.11) • Address, bus cycle indication code and control signals are output in T2 of the prior cycle, instead of the T1 that follows • Compare Figure 9.10 with 9.11 • Fig. 9.11: Address n becomes valid in T2 of prior bus cycle • Fig. 9.11: while data transfer n occurs, address n+1 is output on address bus • 80386 begins accessing the next storage location while it is still performing read/write of data for the previous location • Address-access time: amount of time that address is stable prior to read/write of data • Pipelined mode has longer effective address-access time • Given fixed address-access time (equal speed memory design), pipelined bus cycle will have a shorter duration than nonpipelined busy cycle • I.e. pipelined bus can operate at a higher clock rate than nonpipelined bus cycle. Microprocessors I: Lecture 25

10. Idle State and Wait State • Idle state • no need to access memory • Next bus cycle is not initiated immediately • Wait state (Tw) • Request by an event in external hardware • READY signal (input signal) sampled in the later part of T2 • As long as READY is 1, read/write data transfer does not take place and T2 becomes Tw • Bus cycle is not completed until READY back to 0 Microprocessors I: Lecture 25

11. Read Bus Cycle Timing • Nonpipelined Read Cycle Timing (Figure 9.14) • T1 and T2, each has two phases (1, 2) • 1 of T1 : • Address, BE, ADS (signal a valid address is on address bus) • Bus indication signals (M/IO, D/C, W/R) are made valid • 1 of T2 : • BS16 signal made valid • 2 of T2 : • READY input is tested • Data is ready on data bus, if READY = 0 • Bus cycle extended to Wait state, if READY = 1 Microprocessors I: Lecture 25

12. Microprocessors I: Lecture 25

13. Write Bus Cycle Timing • Nonpipelined Write Cycle Timing (Figure 9.16) • 1 of T1 : • Address, BE, ADS (signal a valid address is on address bus) • Bus indication signals (M/IO, D/C, W/R) are made valid • 2 of T1 : • Outputs the data to be written to memory onto data bus • data made valid until the end of the bus cycle • 1 of T2 : • BS16 signal made valid • 2 of T2 : • READY input is tested • Wait State • Inserted with READY input signal • Duration of Tw = T2 Microprocessors I: Lecture 25

14. Microprocessors I: Lecture 25

15. Next time • Exam 2 Review • Look for review slides soon—be prepared with questions on Monday! Microprocessors I: Lecture 25