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Lecture 7 and 8

Lecture 7 and 8. Extended FSM models (RT-level). FSMs have normally only Boolean inputs as conditions and Boolean outputs Sequential logic has both control path and data path. How to describe? How can we include arithmetic in a FSM? One answer is to use a FSMD (FSM with Data path).

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Lecture 7 and 8

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  1. Lecture 7 and 8 Custom Designed Integrated Circuits

  2. Extended FSM models (RT-level) • FSMs have normally only Boolean inputs as conditions and Boolean outputs • Sequential logic has both control path and data path. How to describe? • How can we include arithmetic in a FSM? • One answer is to use a FSMD (FSM with Data path) Custom Designed Integrated Circuits

  3. X<Y X>Y Y=Y-X X=X-Y Extended FSM Models Control path(FSM) FSMD Status signals Control signals Datapath(ALU etc) Custom Designed Integrated Circuits

  4. s1 s2 =? s3 s4 Control Path Extended FSM Models Control signals Condition signals Data Path Custom Designed Integrated Circuits

  5. Extended FSM Models (FSMD) State name Unconditional variable and output assignments State box Condition 0 1 Decision box Conditional variable assignment Condition box Custom Designed Integrated Circuits

  6. Extended FSM Models (FSMD) s0 s0 Block Block s1 s1 s2 Cond assign Moore type Mealy type Custom Designed Integrated Circuits

  7. Extended FSM, UART Project • We want to model the UART. Alternatives: • Sequential language model (just VHDL) • State machine model (FSM) for control and data path. Control and condition signals between control path and data path. • Extended FSM (FSMD with data path) • Model can be manually synthesized to VHDL code which is automatically synthesized to logic Custom Designed Integrated Circuits

  8. Extended FSM, UART Project Buss interface Bit rate generator Bit rate * 16 Receiver Transmitter FSM FSM RX Reg TX Reg Custom Designed Integrated Circuits

  9. Extended FSM, UART Project Synchronous clock and bit clock Do not gate the clock but use a condition! process begin if reset=‘1’ then ......... elsif clk’eventand clk=‘1’ then if bit_clk=‘1’ then -- bit clock= one clk period ......... end if; end if; end process; Custom Designed Integrated Circuits

  10. FSMD for UART Receiver s2 s0 RXRDY=1 Cnt16=0BitCnt=0 RXRDY-set: Strobe one system clock! 0 RX=0 s1 BitCnt=9 Cnt16=Cnt16+1 0 Cnt16=7 0 R=RX & R(9:1) R=Par & R(9:1) BitCnt=BitCnt+1 Custom Designed Integrated Circuits

  11. Design Productivity Gap Moore’s Law Progress in Design Automation Design Productivity Gap Moore’s Law: The capacity of integrated chips doubles every 18-20 months. 108 106 1 65 75 80 85 90 95 2000 Time Custom Designed Integrated Circuits

  12. History of Automation in System Design Levels of Design Representation System Functional Specification  Behavioral Specification (VHDL)  RTL Design, “C-Code”  Logic Level Design, “Machine Code”  Physical Design  Implementation 2000 Partially 90s 85 80s 70’s Custom Designed Integrated Circuits

  13. Y-Chart Behavioral Domain Structural Domain Flowcharts, Algorithms Register Transfers Processors, Mem, Buses Registers, ALUs, MuXs, . Gates, Flip-Flops - Transistors Boolean Expressions Transistor Functions Transistor Layout Cells, Modules Chips, ASICs Boards, MCM Physical Domain Custom Designed Integrated Circuits

  14. Y-Chart-AXES • Behavioral Axis • Represents functionality: what the system is supposed to do. • Structural Axis • Represents the logical interconnections of components to build the system: how the system is built by interconnecting sub-systems(components). • Physical Axis • Represents the physical implementation of the system. Custom Designed Integrated Circuits

  15. Design Representation in Y-Chart Behavioral Domain Structural Domain Functional Design Flowcharts, Algorithms Register Transfers Processors, Mem, Buses Registers, ALUs, MuXs, . Gates, Flip-Flops - Transistors Boolean Expressions Transistor Functions Transistor Layout Cells, Modules Chip, ASIC Physical Design of a chip • As we move towards the center, we add more details Boards, MCM Physical Domain Custom Designed Integrated Circuits

  16. Representation of Design Processes Behavioral Domain Synthesis Structural Domain Flowcharts, Algorithms Register Transfers Processors, Mem, Buses Registers, ALUs, MuXs, . Gates, Flip-Flops - Transistors Boolean Expressions Transistor Functions Transistor Layout Cells, Modules Chips, ASICs Implementation Boards, MCM Physical Domain Custom Designed Integrated Circuits

  17. High level design / Simulation The efficiency of the designer will increase if she/he designs at a higher abstraction level. It’s possible to design and simulate VHDL on a Behavioural level. The data types etc can be more freely chosen. Special synthesis tools are required to synthesize on behavioural level! Note the difference between behavioural level and behavioural synthesis! We will come to Behavioural synthesis later in this lecture Custom Designed Integrated Circuits

  18. Synthesis Synthesis involves the transformation of system description from behavioral domain to structural domain. • Behavioral Synthesis • Algorithmic description => RTL-design • RTL-design: Design using Registers, adders, muxes etc. • Logic Synthesis • Boolean functions, Finite State Machines => Logic Design • Logic design: Design using gates and flip-flops. Custom Designed Integrated Circuits

  19. Synthesizable/Executable Spec. • Executable Specification It is possible to simulate the specification to determine system behaviour. Some languages give clock accurate simulation (e.g. SystemC). • Synthesizable Specification It is possible to build hardware with equivalent timing and functional behaviour to the specification. (A subset of VHDL is synthesizable) Custom Designed Integrated Circuits

  20. Synthesizable VHDL: Examples Simulation Architecture XYZ of PQR is Signal S1, S2, S3 Begin • • • • • • • • • • S2 <= X and Y; S3 <= S2 or Y after 3 ns; • • • • • • End; Y S2 S3 X Y S2 S3 & 1 It is not possible to ensure the delay to be exact 3 ns. Custom Designed Integrated Circuits

  21. Behavioral and RTL Synthesis Behavioral Synthesis x x - + 4 cycles*15 ns x - + 3 cycles*15 ns x Vary clock period Vary # of clock periods x - + 2 cycles*20 ns x HDL Description Z=a(i)*b(i)-c*d(k)+f Multiple Architectures RTL Synthesis x - + 1 cycle*55 ns x Vary clock period 1 clock cycle Single Architectures Custom Designed Integrated Circuits

  22. MUX MUX X-Reg Y-Reg MUX MUX Comparator - Z-Reg Controller Control Signals Behavioral Synthesis: Illustration ENTITY gcd IS PORT (x_in,y_in: IN bit8; z_out: OUT bit8; clock, start: IN BIT; ready: OUT BIT); END gcd; ARCHITECTURE beh_gcd IS BEGIN PROCESS Variable x,y,z: bit8; BEGIN WAIT UNTIL start = ’1’; X= x_in; Y = y_in; WHILE NOT( X=Y) LOOP IF X > Y THEN X= X- Y ELSE Y = Y-X; WAIT UNTIL clock’event; END LOOP; Z_out = X; ready = ’1’; END Process Custom Designed Integrated Circuits

  23. Behavioral Synthesis/High Level Synthesis Behavioral synthesis translates the behavioral HDL (VHDL) description to RTL-design (Register Transfer Level). Reuse of resources! Control of resource usage done by Control Unit ( comapare to RTL-level) Behavioral Synthesis Steps • Scheduling • To decide time for each operation • Constrains on resources or time • Allocation • Resources: Registers, Memories, ALUs, buses etc. • To decide the type and number of resources required. • Binding • Deciding a specific ALU for each operation • Deciding a specific register for each varible. Custom Designed Integrated Circuits

  24. Behavioral Synthesis/High Level Synthesis • Data path: A number of interconnected components on RTL-level • Control Unit: FSM that generates control signals for Data path • Scheduling To decide time for each operation. Determine in which clock cycle a resource shall be executed. Different function can use the same resource but not at the same time. The scheduler is implemented as a State machine (control unit). • Allocation Allocate resources to operators. Decide the type and number of resources required. • Binding Bind a special resource to a special operation • Latency: Number of clock cycles required to execute a function. • Throughput: How often new data can be clocked into the system. Custom Designed Integrated Circuits

  25. Behavioral Synthesis/High Level Synthesis 1 * * + 2 2 The resources shall be scheduled so the resource with the longest path to end shall be scheduled first. (one method) * 3 * 3 + 4 Custom Designed Integrated Circuits

  26. Behavioral Synthesis/High Level Synthesis • Handshaking / Process synchronization • VHDL code can be correctly simulated on behavioural level. It’s clock accurate. • After Behavioural synthesis the cycle-to-cycle behaviour is changed (due to scheduling and resource allocation). • The processes must be synchronized by handshake signals data ready Custom Designed Integrated Circuits

  27. Behavioural synthesis For special purposes a HW, designed by Behavioural Synthesis, can replace a micro controller and SW (SPP=Single Purpose Processor). Less over headFaster Example: Scheduler in a Real time kernel in HW. RealFast in Västerås Custom Designed Integrated Circuits

  28. Technology Mapping Technology mapping process converts a technology independent design into a netlist of components from a particular technology • Technology independent design (generic) • Gates with any number of inputs or outputs. • Register of any size and with any number of control signals. • Technology dependent components • A gate with 2 inputs and a specified fan-out. • A gate optimized for speed. • A gate optimized for area. • Etc. Custom Designed Integrated Circuits

  29. state A process X process Y state A signals wait for signal send signal state B channel System Modelling C has been used for system modelling and then refined with VHDL. Newer methods: SDL, Specification and Description Language (graphical)SystemC (Class library to C++ for HW modelling) EFSM = Extended Finite State Machine (data path and control path). Control path generated by tool. Custom Designed Integrated Circuits

  30. System Modelling HW and SW co-design and co-simulation. Tools to partion HW and SW New tools or extended “old” tools: Examples C / VHDL 1) SystemC (C++ with class libraries for hardware and communication modelling) 2) Superlog (extended Verilog) 3) Custom Designed Integrated Circuits

  31. IP, Intellectual Property Virtual components / Cores The design efficiency can be increased if tested components are reused. Such virtual components are called IP (Intellectual Property). Hard IP: Technology mapped for a special process or FPGA.Soft IP: Synthesible HDL description (VHDL, Verilog, SystemC etc). Examples of IP blocks : Cores: Micro controllers, DSP, DES encryption modules etc. IO-block: DRAM-controller, UART, USB, Firewire etc Custom Designed Integrated Circuits

  32. CPU USER LOGIC Commu-nication RAM Co Processor IO SoC System On Chip Custom Designed Integrated Circuits

  33. SoC / SOPC System On Programmable Chip New technology (small scale) has high NRE (Nonrecurring Engineering Cost). (1.2 => 0.6 => 0.35 => 0.25 => 0.15 => 0.13 =>0,09 ( ?? m) Today (2003): NRE (0.13 m) $500k-1000k(Write off for a fab is $2Bn+ over 3 years) Q: Who can afford this?A: Big companies with very high volumes.Q: Why do we then study System Level Design? In Sweden only Ericsson designs such circuits.A: FPGAs with built in, hard or soft cores, also require system level design methods. Custom Designed Integrated Circuits

  34. NOC Network on Chip (ING Research) network (packet swiched) switch resourcee.g. CPU 0110 0110 Custom Designed Integrated Circuits

  35. Seems interesting? If System level design seems interesting If Logic synthesis seems interesting If Advanced HW design seems interesting Apply for the Master program in Embedded Systems! Custom Designed Integrated Circuits

  36. ASIC Custom Designed Integrated Circuits

  37. Customer Integrated Circuits ASIC (F)PLD FPGA PAL Gate Array Full Custom Std Cell SoC SoPC CPLD PLD ASIC= Application Specific Integrated Circuit Gate Array= Prefabricated wafer with logic+added interconnections (metal layers). Vol > 10k Standard Cell = Library with components (e.g. gates, multiplexors, flip-flops). Precompiled on transistor level. Vol >100k Full Custom = Transistor level design. Used for analog circuits. SoC = System on Chip. Processors and logic on chip. FPLD = Field Programmable Logic Device. FPGA = Field Programmable Gate Array. >1 milj gates! PLD = Programmable Logic Device CPLD = Complex PLD. <10k gates SoPC = System on Programmable Chip Custom Designed Integrated Circuits

  38. ASIC Design Phases Design • From idea to synthesizable model • From synthesizable model  masks Wafer fabrication • To check the fabricated chip • Slicing of wafer into separate chips wire bonding packaging Fabrication Testing Packaging Custom Designed Integrated Circuits

  39. ASIC Design Phase Design Synthesis and Optimization Fabrication Netlist Validation Place & RouteSimulations Testing GDS-II tape Mask set(Photo masks) Packaging Custom Designed Integrated Circuits

  40. ASIC Fabrication Phase Dia= 4”, 6”, 8”.. etcThickness = 0.5 mm Design Silocon wafers Fabrication Semiconductors fabrication Standard cell & Full custom Testing Metal layers inter- connections Only custom stage in Gate Array Packaging Custom Designed Integrated Circuits

  41. ASIC Fabrication Phase Design Fabrication Test vectors Wafer tests(Probing of pads) Testing Test equipment Connection pads Packaging Chip Wafer Custom Designed Integrated Circuits

  42. ASIC Fabrication Phase Design Scribing(Cutting wafers to chips) chip Fabrication Bonding e.g. wire bonding to lead frame Testing Plastic moulding or ceramic packaging Packagingand test Test of circuits Test vectors Custom Designed Integrated Circuits

  43. n-MOS transistor basics Gate oxide Source Drain Gate Positive voltage on the gate will result in a channel of electrons below the gate oxide (inversion => majority carriers will be replaced with minority carriers). - - - - - - - - - - - - - - - - - - - - - - - - p+ n+ n+ Channel (minority carriers=e-) Custom Designed Integrated Circuits

  44. p_MOS transistor basics Gate oxide Source Drain Gate Negative voltage (relative source) on the gate will result in a channel of holes below the gate oxide (inversion => majority carriers will be replaced with minority carriers). p+ n-well n+ p+ p+ + + + + + + + + + + + + + + + + + + + p+ p+ Custom Designed Integrated Circuits

  45. ASIC Fabrication PhasesLithography Si - substrate Si-oxide Si - substrate Photo resist:Organic polymer. Positive photo resist:soluble after exposure with UV-light (shorter and shorter wavelengths required) photo resist Si - substrate UV -light Glass photo mask Si - substrate Si - substrate etching Custom Designed Integrated Circuits

  46. SiO2 Si-substrate SiO2 Si-substrate n-channel MOSFET SiO2 Si-substrate Etching Doping(diffusion / Ion implantation) Si-substrate n+ n+ Poly silicon SiO2 metal connectors Thin oxide Si-substrate Si-substrate n+ n+ SiO2 Si-substrate Custom Designed Integrated Circuits

  47. in out VDD VSS p+ p+ n+ n+ n+ n-well p+ CMOS inverter in Custom Designed Integrated Circuits

  48. CMOS inverter Vout Vin Custom Designed Integrated Circuits

  49. CMOS inverter Custom Designed Integrated Circuits

  50. a & z b z a b CMOS circuits NAND gate P P N N Custom Designed Integrated Circuits

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