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SRTSC

SRTSC. A LabVIEW based Test and Hardware Configuration System f or SRS. Volkan Gezer Eskisehir Osmangazi University & CERN. Aim of SRT CS. Test of SRS electronics cards for production conformance Configuration or Reconfiguration of parameters

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SRTSC

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  1. SRTSC A LabVIEW based Test and Hardware Configuration System for SRS Volkan Gezer Eskisehir Osmangazi University & CERN

  2. Aim of SRTCS • Test of SRS electronics cards for production conformance • Configuration or Reconfiguration of parameters • To be used both for production (PRISMA) and end-users • Scope: FEC card, ADC card, (Hybrid) • More SRS cards to be added Volkan Gezer - volkan.gezer@cern.ch

  3. SRS test infrastructure • Laptop / PC with LabVIEW 2010 and ethernet cable • SRS Crate-HP or desktop ATX –SRS power • 1 FEC Reference card with 1000BASE-T SFP-ethernet plugin • 1 SRS ADC Reference card • 1 SRS CTF Reference card • 1 HDMI cable A-D* • 2 APV hybrids V4 (Master & Slave) + SAMTEC flat cable • 1 DTC link cable (special) • 1 Ethernet Cross cable • 1 Coaxial cable 50 OHM • 1 LVDS – RJ45 cable (special) • 1 Digital Voltmeter • 1 Xilinx USB programmer head • Xilinx iMPACT programming tool (free WEB version) • SRS FEC Firmware (latest version) * Older versions of hybrids need special HDMI cable Volkan Gezer - volkan.gezer@cern.ch

  4. Test setup overview SRTCS Operator SRS crate ATX power chip HDMI cable Loop cable FEC ADC chip Ethernet FPGA diff LVDS cable CTF Clock and trigger generation dtc cable Volkan Gezer - volkan.gezer@cern.ch

  5. Jumpers and Microswitches Don’t start tests before verification of these Jumper positions Microswitches on ADC Volkan Gezer - volkan.gezer@cern.ch

  6. Firmware Programming Xilinx iMPACT Program lamp must be green! Volkan Gezer - volkan.gezer@cern.ch

  7. Test overview* 1. Basic tests: • Voltages are good • FPGA works • Connectors work (soldered etc…) 2. Functionality tests • SRTCS and Firmware * Tests may not cover 100% functionality in first version Volkan Gezer - volkan.gezer@cern.ch

  8. SRTCSfeatures* • Full range of conformance tests • User-friendly error reporting • Auto-increment serial number • Auto MAC address generation and programming • Fully documented buttons with context help • Save as HTML and/or Print Reports with success or fail messages • Expert mode, enabling manual commands and error decoding. * beta version 1.0a Volkan Gezer - volkan.gezer@cern.ch

  9. SRTCS User Interface Run button on toolbar Volkan Gezer - volkan.gezer@cern.ch

  10. FEC Configuration Password protected increment Volkan Gezer - volkan.gezer@cern.ch

  11. FEC: MAC address allocation • Auto-generation based on serial number • Two types of allocation: • 1k CERN Range: SRS-MAC = 08-00-30-F2-00-00 … 08-00-30-F2-FF-FF • External User: Xilinx MAC range (to be discussed), starting with 00-0A-35 Volkan Gezer - volkan.gezer@cern.ch

  12. Done Finalize Configuration button Volkan Gezer - volkan.gezer@cern.ch

  13. FEC Configuration Report Should be printedafter each successful test and configuration Volkan Gezer - volkan.gezer@cern.ch

  14. A. FEC Card Test Dialog appears for each test button Volkan Gezer - volkan.gezer@cern.ch

  15. A.1.Setup of FEC Front Panel Tests(with Reference CTF) CTF Switch in InternalClockandTriggerMode Volkan Gezer - volkan.gezer@cern.ch

  16. A.2. DTC Link Cross Cable Between J1 and J2 needed for test button “check J1-J2“ J1 J2 Cross cable pinout* *standard ethernet cross cable Volkan Gezer - volkan.gezer@cern.ch

  17. A.3. CTF link cable between CTF OUT and J2 on FEC card& LVDS ClockCable needed for CTF clock test button J2 CTF OUT CTF –J2 special cable pinout LVDS In Volkan Gezer - volkan.gezer@cern.ch

  18. B. ADC Card Test Volkan Gezer - volkan.gezer@cern.ch

  19. B.1.Setup of ADC Card Test requires reference CTF, FEC, and 2 Hybrids Volkan Gezer - volkan.gezer@cern.ch

  20. C. Hybrid Test (planned test screen) • JTAG link to Hybrids OK • All channels work • Chip Works • Pedestal Values are OK • Register configuration OK • Incoming chip data OK Volkan Gezer - volkan.gezer@cern.ch

  21. SRTCS Error reporting Error 1 occurred at srtcs.vi Possible reason(s): LabVIEW: An input parameter is invalid. For example if the input is a path, the path might contain a character not allowed by the OS such as ? or @. ========================= NI-488: Command requires GPIB Controller to be Controller-In-Charge. Volkan Gezer - volkan.gezer@cern.ch

  22. D. Expert -> Expert Tab Volkan Gezer - volkan.gezer@cern.ch

  23. Thank you for listening. Yoursuggestionsarewelcome Volkan Gezer volkan.gezer@cern.ch volkangezer@gmail.com Volkan Gezer - volkan.gezer@cern.ch

  24. Backup Volkan Gezer - volkan.gezer@cern.ch

  25. D. Expert -> UDP Flow Tab 6519: FFFFFFFFAAAAFFFF00000000000000000000000000000001000000000002000000000000000300000000000000040000 0000000050000000000000006000000FF00000000000000FF 6263: FFFFFFFFAAAAFFFF000000000000001000000064000000110000003C0000001200000022000000130000002200000014000000220000001500000037000000160000000A00000017000000000001800000064000000190000001E0000001A0000003C0000001B000000280000001C000000EF0000001D000000FE0000 00010000001900000002000000840000000300000004 6039: FFFFFFFFAAAAFFFF0000000000000000000000030000000100000005000000080000FFFF0000000F00000001 6006 Volkan Gezer - volkan.gezer@cern.ch

  26. ISE iMPACT and Programming You need to turn FEC on for status led of the programmer go green Free version available: http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm Volkan Gezer - volkan.gezer@cern.ch

  27. FEC Voltage test points Volkan Gezer - volkan.gezer@cern.ch

  28. FEC backside test points Volkan Gezer - volkan.gezer@cern.ch

  29. ADC Voltage test points Volkan Gezer - volkan.gezer@cern.ch

  30. SRTCS Block Diagram Volkan Gezer - volkan.gezer@cern.ch

  31. SRTCS: To do Volkan Gezer - volkan.gezer@cern.ch

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