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嵌入式系统 在计算机中应用

嵌入式系统 在计算机中应用

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嵌入式系统 在计算机中应用

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  1. 嵌入式系统 在计算机中应用

  2. 1、什么是DSP? ★DSP英文Digital Signal Processor 即数字信号微处理器。专门用于完成各种实时数字信号处理,可以处理复杂的算法和大规模的数据流。 2、DSP的发展 ★DSP的发展有五十年的历史。 (1)20世纪50-60年代,在通用计算机上进行算法的研究和处理系统的模拟与仿真。信号的处理是模拟的。 (2) 20世纪70年代,为经典的DSP,数字滤波,频谱分析,采用通用计算机。 DSP嵌入式系统在各个领域中的应用

  3. (3) 20世纪80年代,为现代的DSP,采用哈佛结构,将数据与程序存贮空间分开。 (4) 20世纪90年代,为先进的DSP,采用流水线,并行指令,多CPU处理器。 ◆DSP的典型应用领域 ※自动化领域的应用:自适应航行控制、防滑制动器、蜂窝电话、数字无绳电话、发动机控制、全球导航系统、振动分析、搞干扰雷达等。 DSP嵌入式系统在各个领域中的应用

  4. ※家电、消费类:数字音频/电视机、教育玩具、音乐合成器、※家电、消费类:数字音频/电视机、教育玩具、音乐合成器、 UPS、空调、自动监控、PDA等。 ※控制领域应用:磁盘驱动控制、发动机控制、激光打印机、电动机控制、机器人控制、伺服控制等。 ※常用算法应用:自适应滤波、卷积、相关、数字滤波、快速付氏变换、希伯尔变换、波形生成、开窗处理等。 ※图象处理:三维动画、数据图、同态处理、数字图象压缩/传递、模式识别、神经智能、图形工作站。 DSP嵌入式系统在各个领域中的应用

  5. ※工业控制:自动化控制DCS、智能仪表、电力电网※工业控制:自动化控制DCS、智能仪表、电力电网 监控、电力拖动、变频控制等。 ※医学应用:生命监护仪、助听器、CT仪、远程诊疗图象实时处理系统等。 ※军事应用:图象处理、导弹制导、航空/航海导航仪、无人自动驾驶、雷达处理、声纳处理等。 ※通信应用:modem、IP电话、VIOP网关、电视会议、PBX、ADPCM译码、DTMF编解码、3G基站、数据加密。 DSP嵌入式系统在各个领域中的应用

  6. ※语音处理:语音识别、语音增强、语音合成、声码器、语音文本等。※语音处理:语音识别、语音增强、语音合成、声码器、语音文本等。 DSP嵌入式系统在各个领域中的应用

  7. TI DSP产品的介绍和应用

  8. TMS320C5000™ TMS320C6000™ TMS320C2000™ Highest-Performance DSPs in the World Most Control-Optimized DSPs in the World Lowest Power/MIPS DSPs in the World TMS320™ DSP Platforms Achieve Unequivocal Leadership

  9. Application Expertise DrivesPerformance-Tuned DSP Products TI DSPs chosen by 8 of top 10 internet consumer electronic manufacturers TI DSPs in 60% of all digital cell phones TMS320C5000 TI DSPs chosen by 7 of top 8 digital still camera manufacturers TI has 80% of VoIP Gateway market TI DSPs in 80% of IP phone designs TI DSPs used in 8 of the top 10 wireless infrastructures

  10. ’C5000: Power-Efficient Performance Optimizing Performance in Space/Power/Cost Constraints

  11. Software Compatible C54xTM DSP World’s Most Popular DSP Over 400 Million Shipped $4 Billion in Design-ins DSC21/24 DSP Product of the YearInternet Telephony OMAP EDN 2000 Innovation of the Year C55xTM DSP Triple Crown Award Winner C5509 288-400 MIPS Best DSPMicroprocessor Report New! New! New! New! New! VC5470 C5502 400 MIPS VC5471 C5407 80-160 MIPS C5404 80-160 MIPS C5000™ DSP Platform Roadmap C55xTM Multicore C5510 320-400 MIPS C5440 Power-Efficient Performance (Memory + MIPS + Peripherals) C5421 Multicore 200 MIPS C5441 532 MIPS C5420 Multicore 200 MIPS C5416 160 MIPS C5410 100-160 MIPS C5409 80-160 MIPS C5402 100-160 MIPS Time C5401 50 MIPS

  12. Program/Data ROM 4K Words JTAG Test/EmulationControl Program/Data RAM 16K Words D(15-0) Program/Data Buses 22 GP I/O A(19-0) MAC ALU Ch 0 DMA Timer 17 x 17 MPY 40-Bit ALU Ch 1 Timer CMPS Operator(VITERBI) 40-Bit Adder Ch 2 RND, SAT EXP Encoder Ch 3 Host PortInterface (HPI) Peripheral Bus Shifter Accumulators Ch 4 Multichannel BufferedSerial Port (McBSP) 40-Bit Barrel(-16, 31) 40-Bit ACC A Ch 5 40-Bit ACC B Multichannel BufferedSerial Port (McBSP) Addressing Unit 8 Auxiliary Registers PLL Clock Generator 2 Addressing Units S/W WaitstateGenerator Power Management TMS320C5402-100 High Performance • 100 MIPS • 16K words SRAM • 2 McBSPs • 6-channel DMA • 8-bit HPI • 22 GPIO Low Power • 1.8-V core • < 60 mW active power • nW range in standby mode Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm)

  13. Program/Data ROM 16K Words JTAG Test/EmulationControl Program/Data RAM 16K Words Program/Data Buses 26 Muxed GP I/O Ch 0 MAC ALU Ch 1 DMA 8/16-bit Host PortInterface (HPI) 17 x 17 MPY 40-Bit ALU Ch 2 Timer CMPS Operator(VITERBI) 40-Bit Adder Ch 3 RND, SAT EXP Encoder Ch 4 Multichannel BufferedSerial Port (McBSP Peripheral Bus Shifter Accumulators Ch 5 Multichannel BufferedSerial Port (McBSP) 40-Bit Barrel(-16, 31) 40-Bit ACC A 40-Bit ACC B Multichannel BufferedSerial Port (McBSP) Addressing Unit 8 Auxiliary Registers PLL Clock Generator 2 Addressing Units S/W WaitstateGenerator Power Management TMS320C5402A-160 High Performance • 160-MIPS performance • 16K words SRAM • 3 McBSPs • 6-channel DMA • 8/16-bit HPI • 1.2-V and 1.8-V core options Low Power • < 72 mW active power (100 MIPS) Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm) D(15-0) A(22-0)

  14. Program/Data ROM 64K Words JTAG Test/EmulationControl Program/Data RAM 16K Words Program/Data Buses MAC ALU DMA Ch 0 23 Muxed GP I/O 17 x 17 MPY 40-Bit ALU Ch 1 8/16-bit Host PortInterface (HPI) CMPS Operator(VITERBI) 40-Bit Adder Ch 2 RND, SAT EXP Encoder Ch 3 2 Timer Peripheral Bus Shifter Accumulators Ch 4 3 McBSP 40-Bit Barrel(-16, 31) 40-Bit ACC A Ch 5 40-Bit ACC B UART Addressing Unit 8 Auxiliary Registers PLL Clock Generator 2 Addressing Units S/W WaitstateGenerator Power Management TMS320C5404-120 High Performance • 120-MIPS performance • 16K words SRAM • 3 McBSPs • 6-channel DMA • 8/16-bit HPI • UART • 1.5-V core options Low Power • 50 mW active power (120 MIPS) Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm) D(15-0) A(22-0)

  15. Program/Data ROM 16K Words JTAG Test/EmulationControl Program/Data RAM 32K Words Program/Data Buses 26 Muxed GP I/O Ch 0 MAC ALU Ch 1 DMA 8/16-bit Host PortInterface (HPI) 17 x 17 MPY 40-Bit ALU Ch 2 Timer CMPS Operator(VITERBI) 40-Bit Adder Ch 3 RND, SAT EXP Encoder Ch 4 Multichannel BufferedSerial Port (McBSP Peripheral Bus Shifter Accumulators Ch 5 Multichannel BufferedSerial Port (McBSP) 40-Bit Barrel(-16, 31) 40-Bit ACC A 40-Bit ACC B Multichannel BufferedSerial Port (McBSP) Addressing Unit 8 Auxiliary Registers PLL Clock Generator 2 Addressing Units S/W WaitstateGenerator Power Management TMS320C5409-160 High Performance • Up to 160-MIPS performance • 32K words SRAM • 3 McBSPs • 6-channel DMA • 8/16-bit HPI • 1.2-V and 1.8-V core options Low Power • < 72 mW active power (100 MIPS) Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm) D(15-0) A(22-0)

  16. Program/Data ROM 16K Words JTAG Test/EmulationControl Program/Data RAM 64K Words Program/Data Buses MAC ALU DMA Timer Ch 0 17 x 17 MPY 40-Bit ALU Ch 1 Host PortInterface (HPI) CMPS Operator(VITERBI) 40-Bit Adder Ch 2 RND, SAT EXP Encoder Multichannel BufferedSerial Port (McBSP) Ch 3 Peripheral Bus Shifter Accumulators Ch 4 Multichannel BufferedSerial Port (McBSP) 40-Bit Barrel(-16, 31) 40-Bit ACC A Ch 5 40-Bit ACC B Multichannel BufferedSerial Port (McBSP) Addressing Unit 8 Auxiliary Registers PLL Clock Generator 2 Addressing Units S/W WaitstateGenerator Power Management TMS320C5410-160 High Performance • Up to 160 MIPS • 64Kw words SRAM • 3 McBSPs • 6-channel DMA • 8-bit HPI Low Power • 1.5-V core • <80 mW active power (120 MIPS) • nano-Watt range in standby mode Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm) D(15-0) A(23-0)

  17. High Performance 160 MIPS 128K words SRAM 16K words ROM 3 McBSPs 6-channel DMA 8/16-bit HPI Low Power < 90 mW power dissipation 1.5-V core Three power-management modes Small Size 144-pin LQFP Ultra-small 144 microStar™ BGA (12 mm x 12 mm) Program/Data ROM 16K Words JTAG Test/EmulationControl Program/Data SRAM 128K Words D(15-0) Program/Data Buses Muxed GP I/O A(23-0) Ch 0 MAC ALU DMA Timer Ch 1 17 x 17 MPY 40-Bit ALU 8/16-bit Host PortInterface (HPI) CMPS Operator(VITERBI) 40-Bit Adder Ch 2 RND, SAT Ch 3 EXP Encoder Multichannel BufferedSerial Port (McBSP) Peripheral Bus Shifter Accumulators Ch 4 Multichannel BufferedSerial Port (McBSP) 40-Bit Barrel(-16, 31) 40-Bit ACC A Ch 5 40-Bit ACC B Multichannel BufferedSerial Port (McBSP) Addressing Unit 8 Auxiliary Registers PLL Clock Generator 2 Addressing Units S/W WaitstateGenerator Power Management TMS320C5416-160

  18. 100K Words RAM JTAG Test/EmulationControl Program/Data Buses Multichannel BufferedSerial Port (McBSP) DMA MAC ALU Multichannel BufferedSerial Port (McBSP) 17 x 17 MPY 40-Bit ALU Multichannel BufferedSerial Port (McBSP) CMPS Operator(VITERBI) 40-Bit Adder Peripheral Bus RND, SAT EXP Encoder Timer Shifter Accumulators Power Management GP I/O 40-Bit Barrel(-16, 31) 40-Bit ACC A 40-Bit ACC B PLL Clock Generator Addressing Unit Ch 0 Ch 0 8 Auxiliary Registers 16-Bit Host PortInterface (HPI) 2 Addressing Units Ch 1 Ch 1 FIFO Interface Ch 2 Ch 2 MAC ALU Ch 3 Ch 3 17 x 17 MPY 40-Bit ALU 16-Bit Host PortInterface (HPI) 40-Bit Adder CMPS Operator(VITERBI) DMA Ch 4 Ch 4 Multichannel BufferedSerial Port (McBSP) RND, SAT EXP Encoder Shifter Accumulators Ch 5 Ch 5 Multichannel BufferedSerial Port (McBSP) Power Management 40-Bit Barrel(-16, 31) 40-Bit ACC A Multichannel BufferedSerial Port (McBSP) Peripheral Bus 40-Bit ACC B Addressing Unit Timer 8 Auxiliary Registers 2 Addressing Units GP I/O PLL Clock Generator JTAG Test/EmulationControl Program/Data Buses 100K Words RAM TMS320VC5420-200 High Performance • 200 MIPS • 100kw SRAM/Core • (3.2 Mbits total) • 6 McBSPs • 12-channels DMA • 16-bit HPI Low Power • 1.8-V core • < 120 mW active power • nano-Watt range in standby mode Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm)

  19. 64K Words RAM 2KW ROM JTAG Test/EmulationControl Program/Data Buses McBSP DMA McBSP McBSP Peripheral Bus 16-Bit Timer C54x Core Power Management 2 GP I/O PLL Clock Ch 0 Ch 0 16-Bit HPI Ch 1 Ch 1 128K Words RAM FIFO Interface Ch 2 Ch 2 Ch 3 Ch 3 16-Bit HPI Ch 4 Ch 4 DMA McBSP Ch 5 Ch 5 McBSP C54x Core Power Management Peripheral Bus McBSP 16-Bit Timer 2 GP I/O PLL Clock Program/Data Buses JTAG Test/EmulationControl 64K Words RAM 2KW ROM TMS320VC5421-200 High Performance • 200 MIPS (100 MHz / core) • 64kw SRAM/Core; 128 kw shared (4.1 Mbits Total) • 6 McBSPs with 128-channel selection • 12-channels DMA w/ external transfer (256K word) • 16-bit HPI Low Power • 1.8-V core • 160 mW active power@ 200 MIPS Small Size • 144-pin LQFP • Ultra-small 144 microStar™ BGA (12 mm x 12 mm)

  20. Program/Data Buses Program/Data Buses Program/Data Buses 128K words RAM 96K RAM 96K RAM 96K RAM 96K RAM 128K words RAM ROM ROM C54x core C54x core C54x core C54x core Program/Data Buses ROM ROM TMS320VC5441-532 High Performance • 133 MHz per core (532 MIPS) • 640K words SRAM (10.2 Mbits) • 4 McBSPs plus 2 shared • 16-bit HPI Ultra-low power/channel • 1.5-V core • 550 mW active power @ 532 MIPS • 0.15 m process technology Small Size • 176 TQFP • 179 microStar™ BGA (12 x 12 mm)

  21. C54x C55x Mnemonic C54x Mnemonic Higher performance CPU C55x Extending the C5000 Architecture 2 - 40 bit accumulators 1 - 40-bit ALU 1 - 40 bit barrel shifter L31,R16 1 - 17x17-bit MAC unprotected pipeline 1 - 16 bit program bus 3 - 16 bit data buses 4 - 16 bit address buses separate program, data memory 4 - 40 bit accumulators 1 - 40-bit ALU - dual mode + 1 16-bit ALU 1 - 40 bit barrel shifter L32,R31 2 - 17x17-bit MACs protected pipeline 1 - 32 bit program bus 5 - 16 bit data buses 6 - 24 bit address buses unified memory space Extended hardware resources Superset of 54x Mnemonic 8,16,24,32,40,48 bit instructions defined parallel instructions user defined parallel instructions 16 bit instructions defined parallel instructions

  22. Existing C54x Architecture 16-bit data busses P Bus (Coefficient) C Bus D Bus ACC Buss MAC Shifter 40-Bit ALU Splittable ACC A ACC B Address Generators Y X E Bus AR0 AR1 AR2 AR3 CAB EAB 3 Address Busses AR4 AR5 DAB ASM AR6 16-bit 64k words AR7 T-Reg Resources on C54x

  23. C55x: Extends C5000 Capabilities 16-bit data busses B Bus (Coefficient) C Bus D Bus D Registers Interconnect ACC Buss MAC-0 MAC-1 Shifter 40-Bit ALU 16-Bit ALU Splittable AC0 AC1 AC2 Three Address Generators C Y X E Bus AC3 XAR0 AR0 F Bus XAR1 AR1 XAR2 AR2 DR0 XAR3 AR3 CAB EAB 5 Address Busses BAB XAR4 AR4 DR1 AR5 XAR5 DAB FAB DR2 24-bit XAR6 AR6 XAR7 AR7 DR3 Added to C55x Common to C54x XCDP CDP XDP -

  24. 16 KW ROM • Six-channel • DMA Peripherals 6 channel DMA ClockGenerator 3 McBSPs Enhanced HPI 2 Timers C5510: The First 55x Device VC5510 Device Specific Information 160 KW SRAM • 160 KW SRAM • 16 KW ROM • On-Chip Memory CORE Data Read (3-16 bit) • I-Cache • 24 KByte Cache Data Write (2-16 bit) C55xTM CPU Advanced Power Management IdleDomainRegister Instruct Buffer Unit • 3 Multi-channel Buffered Serial Ports • 128 Channels Each Dual Mac ALU Advanced Emulation I-Cache 17 x 17 MPY40-bit ADDRRND, SAT 40-bit CMPS Operator (Viterbi)EXP Encoder • 16-bit • Enhanced HPI 32 bit-EMIF 16-bitALU Program 32 bits • Supports Cheaper & Faster Memories 17 x 17 MPY40-bit ADDRRND, SAT • External Memory Interface (EMIF) Peripherals Bus 4 Data Reg Accumulators • Advanced Emulation BarrelShifter 8 Aux.Reg • Easier Debug 40-bit(-32, 31) 40-bitAcc B 40-bitAcc A 40-bitAcc B • Connect Peripherals • directly to the DSP 3Addr.Units • 8 GP I/O Lines 40-bitAcc C 40-bitAcc D • Package • 240 Ball, 15x15u*BGA TMS320C55xTM

  25. Industry’s most power-efficient performance transforms new applications Two new devices expand the world’s most popular DSP platform with broadest software-compatible roadmap EVMs and complete documentation available today speed time to revenue Power Efficient Performance for $9.95 and Hand-Held Media Processing TMS320C5502 — 400 MIPS at $9.95 in 10ku quantities TMS320C5509 — Portable, connected DSP increasesbattery life by 70% Proven Industry Standard with over 400 Million Units Shipped and over $4B in Designs Start Now! Finish First.

  26. C5509 - The Portable and Connected DSP Data Read (3-16 bit) Data Write (2-16 bit) USB C55xTM DSP CORE I2CInterface Program 32 bits IdleDomainRegister Advanced Power Mgmt Instruction Buffer Unit 10-bit ADC Advanced Emulation MMC/SD 40-bitALU RTC MemStick Dual Mac 16-bit ALU Program 32 bits Reg. EHPI Accumulators AddrUnits 3 McBSPs Barrel Shifter Watchdog 6 channel DMA 32 KW ROM 32 KW DARAM 96 KW SARAM USB 1.1 port 10-bit 500 us ADC for keypad, button and battery monitoring functions Real-Time Clock w/ 32KHz crystal input, separate power Peripherals Memory Stick (MS) Serial Ports MultiMedia Card/Secure Digital (MMC/SD) Serial Ports 3 McBSPs 16-bit EMIF 16 bit-EMIF I2C multi-master and slave interface Peripherals Bus 3 timers: 2 general purpose, 1 watchdog 36/35 GPIO, 8/7 Dedicated (u*BGA/LQFP) 16-bit HPI muxed w/address bus 64-bit unique device ID, secure ROM, JTAG w/ disconnect option for security Peripherals Bus 128K on-chip memory: 32KW DARAM, 96Kw SARAM 2 Timers 8 GPIO DPLL X4 PLL 32KW ROM 144-pin LQFP, 179-pin u*BGA TMS320C5509 @ 144 or 200 MHz

  27. 32KW DARAM 16KW ROM On-Chip Memory 16 KW ROM 32 KW DARAM 128 Channels 100Mbps each 3 Multi-channel Buffered Serial Ports Program 32 bits I2C Interface Glueless interface No software overhead Hardware UART 32 bit-EMIF Program 32 bits C5502 - Price/Performance Leader400MIPS, 500MBps I/O, 90mW, @ $9.95 in 10Ku Low cost SDRAM & SBRAM, Asyn RAM support 400 MBps bandwidth 32-bit External Memory Interface (EMIF) Data Read (3-16 bit) Data Write (2-16 bit) Peripherals 6 channel DMA 16 KByte I-Cache Allows inexpensive memory off chip C55xTM DSP Core 3 McBSPs Internal and externaltransfers Six channel DMA IdleDomainRegister Advanced Power Mgmt Instruction Buffer Unit Watchdog Advanced Emulation 40-bitALU I2C Interface I-Cache 16-bitALU Dual Mac H/WUART Peripherals Bus Registers Enhanced HPI Accumulators 100MBps/ 50MBps 16-bit/8-bit Enhanced Host Port Interface AddressUnits GPIO Barrel Shifter 2 Timers Maximum GPIO to meet system needs 76 GPIO, 8 Dedicated ClockGenerator 176 TQFP 24x24mm 176 µ*BGA 15x15mm Package TMS320C5502 @ 200 MHz

  28. C5401 C5404 C5402 C5407 C5409 C5410 50 120 30/80/100/160 120 30-160 100-160 8K 16K 40K 16K 32K 64K 4K 4K/16K 64K 128K 16K 16K 2 2 3 3 3 3 8-bit 8/16-bit 8/16-bit 8/16-bit 8/16-bit 8/16-bit 6-ch 6-ch 6-ch 6-ch 6-ch 6-ch -- -- -- -- -- -- -- x x -- -- -- -- -- -- -- -- -- 1 2 2 2 2 1 1.5V 1.5V 1.8V 1.5V 1.8V/1.5V 1.5V 40mW(50MHz) 50mW(100MHz) 60mW(100MHz) 50mW(100MHz) 80mW(120MHz) 72mW(100MHz) 144 LQFP144 BGA 144 LQFP144 BGA 144 LQFP144 BGA 144 LQFP144 BGA 144 LQFP144 BGA 144 LQFP144 BGA -- -- -- -- -- -- NOW NOW NOW NOW NOW NOW $3.87 $15.56 $10.02 $5-$9.90 $7.50-$14 $16-19 TI’s C5000™ Power-Efficient DSP Platform SINGLE CORE C5502 Features C5416 C5510 C5509 320-400 MIPS 160 320-400 280-400 RAM 32K 128K 160K 128K 16K 16K 16K 32K ROM 3 3 3 McBSP 3 HPI 8/16-bit 8/16-bit 16-bit 16-bit 6-ch 6-ch DMA 6-ch 6-ch -- -- -- x USB x -- UART -- -- x -- -- x I2C Timer 2 1 2 2 1.5V 1.5V 1.5V 1.6V Core Voltage 90mW(200MHz) 100mW (200MHz) 100mW(200MHz) 90mW(160MHz) Power Package 144 LQFP144 BGA 176 LQFP176 BGA 144 LQFP179 BGA 240 BGA 1Q02 NOW June 01 Samples -- 4Q02 1Q02 Production NOW 1H01 $18.00 $9.95 $24 $27.50 (10KU) Price

  29. UART-IrDA I2C SDRAM & SRAM IF Keypad IF GPIO SPI UART TIMER TIMER-WD TIMER MEM IF DMA McBSP1 McBSP0 JTAG RAM16kb CLKPLL C5471: DSP + ARM TMS320C54x 72kw RAM 2 Multichannel Buffered Serial Port (McBSP) Direct Memory Access controller (DMA) Phase-locked loop External Memory Interface DSP - Interrupt Handler (INTH) ARM Interface (API) 8x8 Keypad C54x DSP100 MIPs LEDs, etc. Codec LCD display RAM72Kw(+API) ARM7TDMI Memory Interface(SDRAM, SRAM, ROM, Flash) ARM - Interrupt Handler (INTH) General purpose I/O (ARMI/O) 16C750 UART-IRDA 16C750 UART Serial Port Interface (SPI) I2C Interface Clock Management (CLKM) 16K byte zero wait-state SRAM DSP SRAM(Optional) RISC - 50 MHz(ARM7TDMI) RISC RAM/ROM PACKAGE: 257 u*BGA 16mm x 16mm

  30. USB LCD Driver MEM IF Video IF GPIO UART TIMER TIMER-WD TIMER CCD Control DMA JTAG Serial I/F CLKPLL DSC21: DSP + ARM TMS320C54x 32kw RAM 1Audio Serial Port Direct Memory Access controller (DMA) Phase-locked loop Image buffers (w/RAM) DSP - Interrupt Handler (INTH) ARM Interface (API) Image RAM Video Block C54x DSP100 MIPs LEDs, etc. Codec CCD Module RAM32Kw(+API) ARM7TDMI Memory Interface(SDRAM, SRAM, ROM, Flash) ARM - Interrupt Handler (INTH) General purpose I/O (ARMI/O) 16C750 UART USB LCD Driver output RGB Clock Management (CLKM) 32K byte zero wait-state SRAM Flash ROM RISC - 50 MHz(ARM7TDMI) RAM32kb RISC RAM SDRAM PACKAGE: 256 u*BGA 16mm x 16mm

  31. Timer (x3) WDT Int Ctrl McBSP (x2) MCSI (x2) GPIO UART1 UART/PWMs Mailbox DMA Traffic Controller / Memory I/F • 100MHz Timer (3) WDT Int Ctrl RTC I2C Host uWire/UART McBSP Keyboard OMAP™ Application Processor OMAP™ Processor Core 55x DSP Subsystem • 200 MHz • 12KW 2x 1-cache • 48KW SARAM • 32KW DARAM • 16KW ROM • Video Accelerators SDRAM ARM925 Subsystem • 175 MHz • 16KB i-cache • 8KB d-cache Flash SRAM UART USB Host/ Client Camera I/F SD/MMC LCD Ctrl Frame Buffer (1.5 Mb) Peripherals

  32. TI’s C5000™ Power-Efficient DSP Platform MULTI-CORE -- C5420 Features C5421 C5441 C5470 C5471 MIPS 200 532 200 100 100 RAM 256K 640K 72K 72K 200K 4K -- -- -- -- ROM 6 12 McBSP 2 2 6 HPI 8/16-bit 16-bit -- 8/16-bit -- 12-ch DMA 12-ch 24-ch 6-ch 6-ch -- -- -- -- USB -- -- -- -- -- UART -- -- -- -- -- -- I2C Timer 2 4 3 3 2 1.8V 1.5V 1.8V 1.8V 1.8V Core Voltage 550mW(133MHz) 200mW(100MHz) 200mW(100MHz) 160mW(100MHz) 266mW(100MHz) Power Package 144 LQFP144 BGA 176 LQFP169 BGA 144 LQFP144 BGA 257 BGA 257 BGA -- Samples -- NOW -- -- Production NOW 3Q01 NOW NOW NOW $60 $100 $17.57 $15.50 (10KU) $50 Price

  33. ’ C5000: Interfacing Variety of sources for easy interfacing Internal Memory External Memory Interface (EMIF) Serial Ports: • Standard Serial Port • Buffered (BSP) • Multi-channel (McBSP) Host Port Interface (HPI) Direct Memory Access (DMA)

  34. Interfacing: Internal memory access Internal Memory Access SARAM ROM DARAM RAM ROM & RAM:One accessper blockper cycle 2K 8K 4K 4K 2K 8K ... ... ... P DARAM:Two accessesper blockper cycle D C MAC ALU

  35. EMIF: Flexible memory I/F • Typical asynchronous parallel interface • Separate strobes for program, dataand I/O spaces • 23-bit address range for externalprogram space • 0-14 software programmable wait states • Simplified bank switching -- programmable ability to insert wait states when crossing bank boundaries

  36. Standard Serial Port: Pins & signals Transmit Receive CLKX FSX DX CLKR FSR DR Clock Frame Data LSB MSB

  37. Standard Serial Port: Architecture RINT XINT CPU Data Bus DRR SPC DXR Control Logic RSR XSR DR DX FSR CLKR CLKX FSX

  38. CPU Buffered Serial Port: Autobuffering • Clocks at full CLKOUT rate • Supports full-duplexed and double-buffered for flexible data stream length • Supports high-speed transfers • Reduces overhead of servicing interrupts Data Memory Receive Buffer BSP DR Autobuffering Unit (ABU) Receiver Transmitter Transmit Buffer DX

  39. RCR XCR RCR BSR RBR DRR MCR SRGR DXR XCR BSR SPCR Overview of McBSP(Multi-channel Buffered Serial Port) • Full-duplex, bi-directional comm • Superset of existing C5x/C54x BSP • Runs at up to 1/2 CPU Clock Rate • Compliant with a Variety of Standards • Double Buffered Transmit, Triple Buffered Receive • H/W u-Law, A-Law companding • Multi-channel transmit and receive of up to 128 channels • Wider selection of data sizes (8-, 12-, 16-, 20-, 24-, or 32-bit) DR EXPAND DX COMPRESS CLKX CLKR CLOCK GEN FRAME SYNC GEN AND CONTROL FSX FSR PERIPHERALBUS CLKS PCR MULTI-CHANNEL SELECTION RINT XINT REVT XEVT

  40. SRGR BSR RBR DRR XCR RCR DXR MCR BSR SPCR RCR XCR McBSP Standards • MVIP and ST-bus compliant • T1/E1 Framing Chips • IOM2 • SPI • IIS • AC97 • Industry Standard Codecs • Analog Interface Chips: TI TLC320 DR EXPAND DX COMPRESS CLKX CLKR CLOCK GEN FRAME SYNC GEN AND CONTROL FSX FSR PERIPHERALBUS CLKS PCR MULTI-CHANNEL SELECTION RINT XINT REVT XEVT

  41. McBSP: Glueless I/F with AC97 AC97 Chip ’C5000 McBSP I/F (TI - TLC320AD90C ) SDATA _IN DR SDATA _OUT DX CLKS BIT_CLK SYNC FSX RESET GPIO

  42. HPI16: Overview • On VC5420 • 16-Bit Version of existing C5x/C54x HPI • Data Movement Supported by DMA Bus • Support of Multiplexed Address Data Hosts (Intel) • Glueless I/F to Standard General Purpose Processors • Motorola 68302, 68360, Power PC 860 • IBM Power PC • Maximum Host access rate of 33 MBps, 25MBps with DMA active

  43. Changes on HPI8 and HPI16 • Thanks to the DMA, the new HPIs allow the Host to access to entire on-chip memory • HRDY is driven by DMA request logic • 5410 HPI (Modified Existing HPI on C5x, C542/8/9) • Addition of extended address support • HOM operation is supported but not recommended except for bootloading • 5420 HPI (HPI16 - A Modified C6x HPI) • 16-bit access instead of 8-bit access • Addition of extended address support • addition of non-multiplexed mode • HOM operation is supported but not recommended except for bootloading • 5402 HPI (Modified Existing HPI on C5x, C542/8/9) • No HOM support • HPI boot occurs when device is out of reset

  44. Interfacing: The HPI concept ’C5000 HOST 0000h CONTROL HPI 10 DataMem HPIC DATA CPU 16 DMABUS HPIA SAM • CLK/6 • 266 Mbps @ 10 ns FFFFh

  45. DMA features • 6 independent channel operation • Data moves: • From / to peripherals, off-chip memory, on-chip memory • Program, Data, and I/O space can be accessed • Low / High priority configurable • rotating scheme ; DMA has higher priority than CPU • 16 or 32 bit data transfers (double word mode) • DMA transfer can synch with McBSP xmit or receive events, timer interrupt, or INT3 • Multi-frame transfer mode available for each channel

  46. HPI McBSPs Internal Data DMA Controller Channel 0 Internal Program Channel 1 Channel 2 Channel 3 CPU Channel 4 Channel 5 DMA: Transfers transparent to CPU • High performance: • Six DMA channels • Data moves from / to peripherals andmemory • DMA higher priority than CPU • Programmable: • Data widths • Priorities • Auto-initialization

  47. External I/O Interface (XIO/XIO2) Overview • 16-Bit Wide • Memory Types Supported • Asynchronous • Address Reach • 8 Meg word for Program space • 64K word for Data space • 64K word for I/O space

  48. GPIO • '5410 • 7 McBSP pins: 5 IO pins, 2 input pins • '5420 • For each core, 7 McBSP pins: 5 IO pins, 2 input pins • For each core, 4 dedicated GPIO pins • '5402 • 7 McBSP pins: 5 IO pins, 2 input pins • 22 dedicated GPIO pins

  49. ’C5000 PLLm/n Clock Interfacing: PLL clock • Instruction rate clock can be derived fromslower external clock. • ’C548 and above are programmable on the fly (32 ratios possible; no device reset required) • PLL clock reduces EMI issues by loweringboard-level clock rate. • Lower cost/frequency oscillator (crystal)are multiplied internally. • Device supports programmable delay for PLL lock time.

  50. TI Extends Breadth of World’s Most Popular DSP Platform C5420 C5421 C5441 Features C5402 C5409 C5410 C5416 30/80/100 16K 4K 2 8-bit 6-ch 2 1.8 V1.2 V 60 mW (100 MHz) 144 TQFP 144 BGA — NOW $5 30/80/100 32K 16K 3 8/16-bit 6-ch 1 1.8 V1.2 V 72 mW (100 MHz) 144 TQFP 144 BGA NOW 4Q99 $10 100/120 64K 16K 3 8-bit 6-ch 1 2.5 V 115 mW (100 MHz) 144 TQFP 176 BGA — NOW $24 160 128K 16K 3 8/16-bit 6-ch 1 1.5 V 90 mW (160 MHz) 144 TQFP 144 BGA 4Q99 3Q00 $30 200 200K — 6 16-bit 12-ch 2 1.8 V 266 mW (100 MHz) 144 TQFP 144 BGA — NOW $50 200 256K 4K 6 8/16-bit 12-ch 2 1.8 V 160 mW (100 MHz) 144 TQFP 144 BGA 1/00 2Q00 $80 532 640K 8K 6 8/16-bit 24-ch 4 1.5 V 550 mW(133 MHz) 176 TQFP 179 BGA 3Q00 4Q00 $170 MIPS RAM(words) ROM (words) McBSP HPI DMA Timer CoreVoltage Power Package Samples Production Price (50 KU)