Codesign of Embedded Systems

1. Codesign of Embedded Systems Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {Email: chunghaw@cs.nthu.edu.tw}

2. Outline • Introduction • Implementation technologies • Design technologies • Summary Ref: Rolf Ernst, “Codesign of Embedded Systems: Status and Trends, IEEE Design and Test of Computers, pp. 45-54, April-June, 1998.

3. Introduction Embedded IC revenues (B$) Embedded systems: • Executes specific tasks within larger electronic device • Found in nearly everything electric - cars, office automation, PDA’s, home electronics, factory control Source: Dataquest

4. Embedded system characteristics • Fixed functionality • I/O intensive, reactive • Multiple processes • Time constraints • Low cost ($8-$100), low power (.5-4W), small size

5. ASIP DSP uP Code A/D D/A SAP DSP Code ASIC uC RTOS uP A typical embedded system structure Memory I/O

6. Implementation technologies(Processor types) • Micro-processor and micro-controller • ASIP - application-specific instruction-set processor • DSP - digital signal processor • SAP - single-application processor • ASIC - application-specific integrated circuit

7. Implementation technologies(Package types) • Full-custom IC • Cell-based IC • Gate array • PLD - FPGA • SOC (System-on-a-chip) - core-based design, Intellectual property (IP), system-level integration (merging hw/sw onto 1 chip)

8. Requirements definition Specification System architecture development HW development Interface design SW development Integration & test Embedded-system design process Customer/ marketing Support (CAD, test) System architect Reused comp. Source: Ernst (IEEE D & T of Computer)

9. Two types of codesign uP/SAP-based design System Vertical partitioning Application-specific coprocessors Core processor SW HW

10. System Application SW + simulator, compilers, OS Application-specific processors Two types of codesign ASIP-based design SW Vertical partitioning HW

11. Design technologies • Design specification, modeling, and capture • Synthesis - system-level, RTL, logic level, physical level. • Design space exploration • Design verification and testing.

12. Specification and modeling • Executable specification - Verilog, VHDL, C, C++, Java. • Common models: synchronous dataflow (SDF), sequential programs (Prog.), communicating sequential processes (CSP), object-oriented programming (OOP), FSMs, hierarchical/concurrent FSM (HCFSM). • Depending on the application domain and specification semantics, they are based on different models of computation.

13. Hardware Synthesis • Many RTL, logic level, physical level commercial CAD tools. • Some emerging high-level synthesis tools: the Behavioral Compiler (Synosys), Monet (Mentor Graphics), and RapidPath (DASYS). • Many open problems: memory optimization, parallel heterogeneous hardware architectures, programmable hardware synthesis and optimization, and communication optimization.

14. Software synthesis • The use of real-time operating systems (RTOSs) • The use of DSPs and micro-controllers - code generation issues • Special processor compilation in many cases is still far less efficient than manual code generation! • Retargeting issues - C code developed for the TI TMS320C6x is not optimized for running on Philips TriMedia processor.

15. Software synthesis (Cont.) • The porting is worse when using parallel compilers because of architecture specialization. • Using libraries of predefined and parameterized code modules adapted to an application: SPW and the Mentor Graphics DSP Station.

16. Interface synthesis • Interface between: - hardware-hardware - hardware-software - software-software • Timing and protocols • Has been neglected for a long time in commercial tools • Recently, first commercial tools appeared: the CoWare system (hw-sw protocols) and the Synopsys Protocol Compiler (hw interface synthesis tool)

17. Synthesis: status and trends • Many tools reach a high degree of automation for specific applications; however, many design tasks still need to be done manually • Lacking the ability of exploiting the design space to obtain an optimized solution • IP-based (core-based) synthesis methodology

18. Design space exploration • Process transformation • Hardware/software codesign tasks • Estimation • Manual/automated/assisted

19. Cospecification Process transformation Reused functions and processes System analysis HW/SW partitioning and scheduling HW arch & comp. HW synthesis SW synthesis Reused HW & SW components Evaluation (cosimulation) Design space exploration process Customer/marketing system architect High-level transformation System architect Design space exploration space Source: Ernst (IEEE D & T of Computer)

20. Process transformation • Communication transformation • Process merging • Granularity adaptation • Process retargeting : e.g., a RISC -> a DSP

21. Granularity effects Optimization potential Communication overhead Granularity Analysis Process no(explicit) Function/ Global global data data flow Basic block/ Global and local local data set data flow Statement/ Global and local variables data flow Design effort

22. HW/SW codesign • Hardware-software partitioning • Communication synthesis • Hardware-software scheduling • Memory optimization • Estimation • Cosimulation

23. Communication synthesis • Communication channel selection • communication channel allocation • communication channel scheduling • Currently, no tool can cover the whole variety of communication mechanisms

24. HW/SW scheduling • Static scheduling • Derived from RTOSs - e.g., static table-driven and priority-based preemptive scheduling • Static scheduling for event-driven reactive systems • Distributed scheduling policies for complex embedded architectures

25. Memory optimization • Dominant cost factor in integrated systems and the bottlenecks in system performance • Program cache optimization techniques • Optimization for architectures with memories of different types - such as scratch-pad SRAM and DRAM • Dynamic memory allocation

26. Estimation • Accuracy VS. fidelity • Simulation based • Fast synthesis based

27. Cosimulation • Simulate processor software along with custom hardware • Simulation speed, compile time, debugging capability, test vector creation • Speed VS. accuracy - rate accurate, functionally accurate, cycle accurate, gate accurate

28. Simulator categorization • General-purpose simulator - event-driven • Uni-purpose simulator - designed to simulate a specific model (e.g., 80586) • Emulator - Logic emulator - Processor emulator - In-circuit emulator (ICE)

29. Common cosimulation approaches • HDL simulator • Simple to implement • Slow • Foreign software debug environment

30. Common cosimulation approaches • Linking software processor simulator and HDL simulator • Eagle-I (Mentor Graphics), Seamless (Viewlogic) • Ptolemy (UC Berkley) -- OO software framework for linking simulators • Faster, native software debug environment

31. Common cosimulation approaches • Linking processor emulator and logic emulator • Fast • In-circuit debugging • Expensive • Quickturn

32. Design verification and testing • Closely-coupled design, verification, and testing methodologies • Integrating multi-level design, verification, and testing design tasks • Cosimulation, coemulation, design for test • Rapid prototyping

33. Rapid prototyping • Custom-designed prototyping board • Logic emulators • Field-programmable PCBs

34. Development without prototyping SW Design Code Integration Debug Design Build Integration Debug Debug Fab Design

35. Development with prototyping System Integration & SW Debug Design Code SW Final Integration HW Integration & Debug Design Build HW Chip debug Fab Design CHIP

36. Summary • Embedded systems market is big and growing • Computer-aided hardware-software codesign has made considerable progress in the past few years • System analysis is in great demand - cosimulation, coverification and cospecification • Cosynthesis and computer-aided design space exploration are just beginning to reach the industrial practice