Foundation of Systems

1. Foundation of Systems Xiang Lian The University of Texas-Pan American

2. Digital Computers Only knows binary bits: 0 and 1 (there are only 2 types of people in the world: those who understand binary, and those who don’t)

3. Binary to Decimal (xnxn-1…x0)2=xn×2n+xn-1×2n-1+…+x0×20 Xn: Most significant bit (MSB) X0: Least significant bit (LSB) Ex: (101) 2=1×22+0×21+1×20=4+0+1=5

4. Decimal to Binary Ex: 11 binary number? 11/2: 1 (remainder) 5/2: 1 2/2: 0 1/2: 1 0 : STOP (1011)2

5. Binary Addition-Two Bits 1 + 1 11 1 + 0 01 0 + 1 01 0 + 0 00 Carry bit Exercise: verify that they are correct in terms of decimal integers.

6. Binary Addition-Three Bits 1 + 1 1 11 1 + 0 1 10 0 + 1 1 10 0 + 0 1 01 Exercise: verify that they are correct in terms of decimal integers. 1 + 1 0 10 1 + 0 0 01 0 + 1 0 01 0 + 0 0 00

7. Binary Addition: Bit-wise Addition Step 1: adding the rightmost bits, and recording the carry bit 1011 + 1111 ????? 101 1 + 11111 ???? 0 Step 2: adding the next bits (to the left) with the carry bit, and recording the carry bit 10 1 1 + 111111 ??? 1 0 Step 3: continue Step 2 until all bits are added. (finish it) 1 0 11 + 111111 ?? 0 10

8. Exercise (Binary Addition) 100111 + 110011 ???????

9. Finite Bits Computer use finite bits to represent integers. • So only finite integers can be represented. Ex: 2 bits can only represent 0, 1, 2, 3. • So overflow exists(finite bits are not sufficient) Ex: (10)2+(11) 2=(110) 2?

10. Finite Bits Computer use finite bits to represent integers. • So only finite integers can be represented. Sln: use 8, 16, 32, 64, etc bits (integers needed in our life can be represented) • So overflow exists(finite bits are not sufficient) What to do: depend on applications Who is responsible: systems, programmer, users.

11. More Complicated: Negative Numbers -3 binary number? Sln: use extra bit for sign (sign bit), 0: + and 1: - Ex. (00)2=+0 (10)2=-0 (01)2=+1 (11)2=-1 Problems Two 0s (+0 and -0) Not easy to add positive and negative numbers

12. Negative Numbers: 2’s Complement Note: Xn not only represents sign, but has weights (different to the previous sign-magnititude representation). (xnxn-1…x0)2=-xn×2n+xn-1×2n-1+…+x0×20 Ex: (00)2= =-0×21+0×20=0 (01)2= =-0×21+1×20=1 (10)2= =-1×21+0×20=-2 (11)2= =-1×21+1×20=-1 Good: only one zero Easy to add negative and positive numbers Two useful operations: negation and sign-extending Exercise: (11)2 +(01)2=? (11)2 +(10)2=?

13. 2’s Complement: Negation (011)2=3 binary number of -3? (100)2 : complement of (011)2 +(001)2 : plus one =(101)2 : -3 Exercise: find the negation of (110)2 and (100)2

14. 2’s Complement: Sign Extension Extend (001)2 to 6 bits ?????? (???001) 2 : copy the old bits to the right (000001) 2 : MSBthe remaining bits Exercise: extending (101)2 to 6 bits and verify that they are the same integer.

15. Exercise • Using 8 bits to represent integers. • Add 100 and -55 • Add -55 and -80 • Find negation of 100 • Sign extending -100 to 16 bits.

16. Digital Computers • Knows only binary bits (commands to control computers), which difficult for people to handle. • Therefore, assembly languages were developed for people to control computers. • In this textbook, we learn MIPS.

17. MIPS • An Instruction Set Architecture (ISA): a set of instructions(commands) • Provides interface for programmers • Different implementations may support the same ISA • More see WIKI, MIPS Technology, Yahoo Finance.

18. Instruction Normally requires • Operation (what to do: addition, and, jump, etc) • Operands (what to work on: register, memory, immediate numbers) Ex: • add $s1, $s2, $s3: $s1=$s2+$s3 Operation: add Operands: $s1 (target), $s2 and $s3 (source)

19. Instruction Operands-Registers sub $s1, $s2, $s3: $s1=$s2-$s3 s $s2 $s1 $s3 Registers Processor After the execution of the sub instruction, $s1 holds 9 [=4-(-5)] 5 × 9 4 -5

20. Instruction Operands-Memory Lw $s1, 20($s2): $s1mem[20+$s2] $s2 $s1 $s3 Registers Word Address Processor Memory 5 × ? 4 -5 2 1 3 4 0 0 1 1 34 24 After the instruction, $s1 holds 1×216+1×28+34=65826

21. Instruction Operands-Immediate Number addi $s1, $s2, 20: $s1=$s2+20 $s2 $s1 $s3 Registers Processor 5 × 24 4 -5 After the instruction, $s1 holds 4+20=24 Instruction registers Addi $s1, $s2, 20

22. Instruction Operands-Questions • Why register operands Ans: for performance: registers are the fastest to access by CPU • Why memory operands Ans: for performance: only a few registers for which fast access is possible, then the other data must be in memory • Why immediate operands Ans: for performance: these numbers can be encoded in instruction, no need to access registers/memory

23. Instruction Operations-Arithmetic • Add $s1,$s2,$s3: $s1=$s2+$s3 • Sub $s1,$s2,$s3: $s1=$s2-$s3 • Addi $s1,$s2, 20: $s1=$s2+20 Exericse: • For $s1=1,$s2=2,$s3=3, write the results after executing each instructions. • Write an instruction so that $s1=$s1-1.

24. Instruction Operations-Data Transfer • Lw $s1, 30($s2): $s1mem[$s2+30] (load/read word from memory) • Sw $s1, 20($s2): $s1mem[$s2+20] (store/write a word to memory) • Lb $s1, 30($s2): $s1mem[$s2+30] (load/read a byte from memory) Exercise: read a word/byte at $s2+20 in memory to $s2.

25. Word vs. Byte Address Byte address Word address 00000000 Memory 00000000 2 Aligment restriction: Word address must be a multiple of 4 (the last two bits are 00) 00000001 3 00000010 10 00000011 1 00000100 00000100 5 00000101 3 00000110 22 00000111 4 00001000 00001000 0

26. Word Value-Big/Little Endian Word address Word value at address 00000000? Memory 00000000 2 • big-endian: • Value is : 2×224+3×216+10×28+1=33753601 3 2 3 10 1 10 1 00000100 5 • little-endian: • Value is : 1×224+10×216+3×28+2=17433346 3 1 10 3 2 22 4 00001000 0

27. Data Transfer-Exercise Byte address Suppose $s1 holds the address 0x00000000. Write instructions to swap the integers at address 0x00000000 and 0x00000100. Draw the memory contents after the swap. Memory 00000000 2 00000001 3 00000010 10 00000011 1 00000100 5 00000101 3 00000110 22 00000111 4 00001000 0

28. Instruction Operation-Logical • And • And $s1,$s2,$s3 • Or • Or $s1,$s2,$s3 • And immediate • Andi $s1,$s2,20 • Shift left logic • Sll $s1, $s2,10 • Etc.

29. Logical Operation-And (Two Bits) The following table specifies And operations.

30. Logical Operation-And (Bit-Wise) 1010 and 1110 ???? 1010 and 1110 ???0 For two binary numbers, and each bit independently (no carry bit like in addition) 1010 and 1110 ??10 Continue and finish the example

31. Logical Operation-Or (Two Bits) The following table specifies Or operations.

32. Logical Operation-Or (Bit-Wise) 1010 or 1110 ???? 1010 or 1110 ???0 For two binary numbers, or each bit independently (no carry bit like in addition) 1010 or 1110 ??10 Continue and finish the example

33. Logical Operation-Sll Sll $s1, $s1,3 11110000111100001111000011111111 111 10000111100001111000011111111 000

34. Logical Operation-Exercise • $s1=00000000 00000000 00000000 00001001 $s2=00000000 00000000 00000000 00001100 • What is in $s1 after the following operation (independently) • Sll $s1, $s1,4 • Srl $s1,$s1,4 • And $s1,$s2,$s1 • Or $s1,$s1,$s2 • Andi $s1,$s2,8

35. Instruction Operation-Conditional Branch • Branch if equal • Beq $s1, $s2, 25 • Branch if not equal • Bne $s1, $s2, 25 • Set on less than • Slt $s1,$s2,$s3 • Set on less than unsigned • Sltu $s1,$s2,$s3 • Set on less than immediate • $slti $s1,$s2,20

36. Conditional Branch-Beq • Beq $s1, $s2, 25 $s2 $s1 Word Address Processor Memory 4 4 -5 Beq $s1, $s2, 25 24 add $s1,$s2,$s3 28 Now pc=24, and $s1=$s2, then pc Changes to pc+4+25×4=128 pc 24 Beq $s1,$s2,25 Instruction registers Sub $s1,$s2,$s3 128

37. Conditional Branch-Beq (Cont.) Then next instruction to execute is from address 124. • Beq $s1, $s2, 25 $s2 $s1 Word Address Processor Memory 4 4 -5 Beq $s1, $s2, 25 24 add $s1,$s2,$s3 28 Now pc=24, and $s1=$s2, then pc Changes to pc+4+25×4=128, pc 128 Sub $s1,$s2,$s3 Instruction registers Sub $s1,$s2,$s3 128

38. Conditional Branch-Bne • Bne $s1, $s2, 25 $s2 $s1 Word Address Processor Memory 5 4 -5 Beq $s1, $s2, 25 24 add $s1,$s2,$s3 28 Now pc=24, and $s1≠$s2, then pc Changes to pc+4+25×4=124 pc 24 Beq $s1,$s2,25 Instruction registers Sub $s1,$s2,$s3 128

39. Conditional Branch-Bne (Cont.) Then next instruction to execute is from address 124. • Beq $s1, $s2, 25 $s2 $s1 Word Address Processor Memory 4 4 -5 Beq $s1, $s2, 25 24 add $s1,$s2,$s3 28 Now pc=24, and $s1≠$s2, then pc Changes to pc+4+25×4=128, pc 128 Sub $s1,$s2,$s3 Instruction registers Sub $s1,$s2,$s3 128

40. Conditional Branch-Slt • Slt $s1, $s2, $s3 $s2 $s1 $s3 $s2!<$s3, so $s1=0. Processor 4 4 -5 × 0 For this configuration and instruction slt $s1,$s3,$s2, however, $s1=1, since $s3 <$s2 Slt $s1,$s2,$s3 Instruction registers

41. Conditional Branch-Sltu • Sltu $s1, $s2, $s3 $s2 $s1 $s3 $s2<$s3 when $s3 is an unsigned integer, so $s1=1. Processor 4 4 -5 × 1 For this configuration and instruction slt $s1,$s3,$s2, however, $s1=0, since $s3 !<$s2 Slt $s1,$s2,$s3 Instruction registers

42. Conditiona Branch-Exercise Word Address Write an instruction for address 124 which jumps to the instruction at address 200 • when $s1<$s2. • When $s1==$s2. • When $s1!=$s2 • When $s1>$s2 Memory Instruction 1 124 add $s1,$s2,$s3 128 Sub $s1,$s2,$s3 200

43. Instruction Operation-Unconditional Jump • Jump register • Jr $ra • Jump • J 2500 • Jump-and-link instruction • Jal 2500

44. Unconditional Jump-Jr • Jr $ra $s2 $s1 $ra Word Address Processor Memory 5 4 -5 124 Jr $ra 24 add $s1,$s2,$s3 28 Now $ra=124, then pc =$ra=124 pc 24 Jr $ra Instruction registers Sub $s1,$s2,$s3 124

45. Unconditional Jump-Jr(Cont.) Then next instruction to execute is from address 124. • Jr $ra $s2 $s1 $ra Word Address Processor Memory 4 4 -5 124 Beq $s1, $s2, 25 24 add $s1,$s2,$s3 28 Now $ra=124, then pc =$ra=124 pc 124 Sub $s1,$s2,$s3 Instruction registers Sub $s1,$s2,$s3 124

46. Unconditional Jump-J • J 25 $s2 $s1 $ra Word Address Processor Memory 5 4 -5 124 J 25 24 add $s1,$s2,$s3 28 Now $pc=24 and the immediate number is 25, then pc =100 pc 24 J 25 Instruction registers Sub $s1,$s2,$s3 100

47. Unconditional Jump-J (Cont.) Then next instruction to execute is from address 100. • J 25 $s2 $s1 $ra Word Address Processor Memory 5 4 -5 124 J 25 24 add $s1,$s2,$s3 28 Now $pc=24 and the immediate number is 25, then pc =100 pc 100 Sub $s1,$s2,$s3 Instruction registers Sub $s1,$s2,$s3 100

48. Addressing Mod of J • In the previous example, Why is the target address 100 not 25? • Because J use Pseudodirect addressing mode Pc (32 bits) Immediate number (26 bits) 00000000 00000000 00000000 00011000 00 00000000 00000000 00011001 Target address (32 bits) 00000000 00000000 00000000 01100100 Copy the leftmost 4 bits from pc, 26 bit from the immediate number, And then fill 00 in the last two bits

49. Unconditional Jump-Jal • Jal 25 $s2 $s1 $ra Word Address Processor Memory 5 4 -5 124 Jal 25 24 add $s1,$s2,$s3 28 Now $pc=24 and the immediate number is 25, then $ra=pc+4=28 and pc =100 pc 24 Jal 25 Instruction registers Sub $s1,$s2,$s3 100

50. Unconditional Jump-Jal(Cont.) • Jal 25 $s2 $s1 $ra Word Address Processor Memory 5 4 -5 28 Jal 25 24 add $s1,$s2,$s3 28 Now $pc=24 and the immediate number is 25, then $ra=pc+4=28 and pc =100 pc 100 Sub $s1,$s2,$s3 Instruction registers Sub $s1,$s2,$s3 100