1 / 22

ZigBee Data Depackager

ZigBee Data Depackager. Group members: Cheng Peng and Patrice Umenne Supervisor: Bengt Oelmann. Introduction. ZigBee is a new wireless protocol that works well in sensors, remote monitoring and portable electronics Uses a low data rate of 250 kbps

lcrandall
Télécharger la présentation

ZigBee Data Depackager

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ZigBee Data Depackager Group members: Cheng Peng and Patrice Umenne Supervisor: Bengt Oelmann

  2. Introduction • ZigBee is a new wireless protocol that works well in • sensors, remote monitoring and portable electronics • Uses a low data rate of 250 kbps • Long battery life due to low data rate

  3. Introduction

  4. Protocol overview • The four main frames used for communication in the IEEE 802.15.4 standard are: • Beacon Frame • Acknowledgement Frame • MAC Command Frame • Data Frame

  5. Beacon Frame

  6. Acknowledgment Frame

  7. MAC Command Frame

  8. Data Frame

  9. Microprocessor 8 bits address 8 bits data Request Acknowledge Baseband Decoder ZigBee Data Depackager 8 bits data RTS RTR System Structure • Overall Block

  10. State flow diagram Asynchronous reset Counter1, CRC initialized RTS Ready to Send Signal Tested for incoming data Counter 1 incremented in loop until sixth byte Sixth byte is frame length A crc_reg_initialize =1, counter1_rst = 1, counter1_en = 1 r_w = 1 counter1_en = 1, r_w = 1, comparator1_en = 1 B N rts = 1 ? Y counter1_en = 1, comparator1_en = 1, rtr = 1, counter1_trigg = 1, r_w = 1 C C1 counter1_en = 1, comparator1_en = 1, r_w = 1 counter1_en = 1, comparator1_en = 1, r_w = 1 C2 N comparator1_output = 1? Y

  11. State flow diagram Frame length Byte written to address 128 Counter2 initialized with Frame value RTS signal tested Counter2 decremented in loop to address the RAM on Every new byte Each byte written to RAM Each Byte enters CRC Counter2 Tested to have addressed ”0” Location multiplexer_select_address = 01, address_loc = 10000000, r_w = 1 D multiplexer_select_address = 01, counter2_en = 1, counter2_initialize = 1, r_w = 0 D1 rts = 1? Y counter2_en = 1, counter2_trigg = 1, crc_reg_en = 1, rtr = 1, r_w =1 E counter2_en = 1, crc_reg_en = 1, crc_reg_trigg = 0, r_w=1 E1 counter2_en = 1, crc_reg_en = 1, crc_reg_trigg = 1 E2 r_w = 1, crc_reg_en = 1, counter2_en = 1 F counter2_output = 0? N N rts = 1? Y Y

  12. State flow diagram r_w= 1, crc_reg_en = 1, latch_in_h = 1, latch_in_l = 1 G CRC Checksum Low Byte Written to RAM location 129 CRC High Byte written to location 130 r_w = 1, latch_out_l = 1, multiplexer_select_data = 10, address_loc = 10000001, multiplexer_select__address = 01 H r_w=1, multiplexer_select_data =10, address_loc=10000001, multiplexer_select__address =01 H1 multiplexer_select_data =10, address_loc=10000001, multiplexer_select__address =01 H2 r_w=1, latch_out_h=1, multiplexer_select_data =01, address_loc=10000010, multiplexer_select__address =01 I r_w=1, multiplexer_select_data =01, address_loc=10000010, multiplexer_select__address =01 I1 multiplexer_select_data =01, address_loc=10000010, multiplexer_select__address =01 I2

  13. State flow diagram Microprocessor sends request which is tested Acknowledgement to read reply Continous read cycle until unique address to status register informs controller to exit read cycle to First state multiplexer_select__address =10, r_w=1 request = 1? N Y r_w=1, multiplexer_select__address =10, ack=1 N exam_microprocessor = 0? Y

  14. Testbench Simulation Wave Diagrams

  15. Testbench Simulation

  16. Testbench Sim

  17. Testbench Sim

  18. Testbench Sim

  19. System Verification

  20. CRC Verification

  21. Conclusion and Future Work The depackager receives byte data, stores and calculates an error checksum. Then allows the Microprocessor to read stored data. Future Work would involve coding the processor to read Frame data, process Frame contents and extract data payload to sensor nodes

More Related