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Packet FIFO Q & A

Packet FIFO Q & A. Packet Features are enhanced packet management controls (Mark, Restore and Release functions) that facilitate packet retransmission or receive packet discard functionality. Packet FIFO designs utilize a single synchronous clock domain for the input and output sides.

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Packet FIFO Q & A

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  1. Packet FIFO Q & A • Packet Features are enhanced packet management controls (Mark, Restore and Release functions) that facilitate packet retransmission or receive packet discard functionality. • Packet FIFO designs utilize a single synchronous clock domain for the input and output sides.

  2. Four Configurations of PLB IPIF

  3. Device utilization summary: • --------------- • Selected Device : 2vp100ff1704-6 • Number of Slices: 2147 out of 44096 4% • Number of Slice Flip Flops: 2092 out of 88192 2% • Number of 4 input LUTs: 3844 out of 88192 3% • Number of bonded IOBs: 758 out of 1040 72% • Number of BRAMs: 4 out of 444 0% • Number of GCLKs: 1 out of 16 6% • Timing Summary: • --------------- • Speed Grade: -6 • Minimum period: 9.041ns (Maximum Frequency: 110.607MHz) • Minimum input arrival time before clock: 7.528ns • Maximum output required time after clock: 7.122ns • Maximum combinational path delay: 6.753ns Wishful Configuration

  4. Device utilization summary: • --------------- • Selected Device : 2vp100ff1704-6 • Number of Slices: 1797 out of 44096 3% • Number of Slice Flip Flops: 1806 out of 88192 1% • Number of 4 input LUTs: 3261 out of 88192 3% • Number of bonded IOBs: 752 out of 1040 72% • Number of BRAMs: 4 out of 444 0% • Number of GCLKs: 1 out of 16 6% • Timing Summary: • --------------- • Speed Grade: -6 • Minimum period: 8.645ns (Maximum Frequency: 115.680MHz) • Minimum input arrival time before clock: 7.519ns • Maximum output required time after clock: 7.257ns • Maximum combinational path delay: 6.489ns Reasonable Configuration

  5. Device utilization summary: • --------------- • Selected Device : 2vp100ff1704-6 • Number of Slices: 375 out of 44096 0% • Number of Slice Flip Flops: 592 out of 88192 0% • Number of 4 input LUTs: 543 out of 88192 0% • Number of bonded IOBs: 541 out of 1040 52% • Number of BRAMs: 4 out of 444 0% • Number of GCLKs: 1 out of 16 6% • Timing Summary: • --------------- • Speed Grade: -6 • Minimum period: 6.385ns (Maximum Frequency: 156.617MHz) • Minimum input arrival time before clock: 6.666ns • Maximum output required time after clock: 6.915ns • Maximum combinational path delay: 6.208ns Barebone 1 Configuration

  6. Device utilization summary: • --------------- • Selected Device : 2vp100ff1704-6 • Number of Slices: 338 out of 44096 0% • Number of Slice Flip Flops: 546 out of 88192 0% • Number of 4 input LUTs: 465 out of 88192 0% • Number of bonded IOBs: 537 out of 1040 51% • Number of BRAMs: 4 out of 444 0% • Number of GCLKs: 1 out of 16 6% • Timing Summary: • --------------- • Speed Grade: -6 • Minimum period: 6.359ns (Maximum Frequency: 157.270MHz) • Minimum input arrival time before clock: 6.467ns • Maximum output required time after clock: 6.915ns • Maximum combinational path delay: 6.184ns Barebone 2 Configuration

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