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S ynthesis of Communication Schedules for TTEthernet -based Mixed-Criticality Systems

S ynthesis of Communication Schedules for TTEthernet -based Mixed-Criticality Systems. Domițian Tămaș- Selicean 1 , Paul Pop 1 and Wilfried Steiner 2 1 Technical University of Denmark 2 TTTech Computertechnik AG. Outline . Motivation TTEthernet ARINC 664p7 “Aircraft Data Network ”

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S ynthesis of Communication Schedules for TTEthernet -based Mixed-Criticality Systems

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  1. Synthesis of Communication Schedules forTTEthernet-based Mixed-Criticality Systems Domițian Tămaș-Selicean1,Paul Pop1 and Wilfried Steiner2 1Technical University of Denmark 2TTTech Computertechnik AG

  2. Outline • Motivation • TTEthernet • ARINC 664p7 “Aircraft Data Network” • TT and RC Traffic Transmission • Problem Formulation • Motivational Example • Optimization Strategy • RC End-to-End Analysis • Experimental results • Conclusions

  3. Motivation • Real time applications implemented using distributed systems Point-to-point connection Bus connection PE Application A1 -- highly critical • Reduces wiring and weight • Mixed-criticality applications share the same network Application A 2 -- critical Application A3 -- non-critical

  4. ARINC 664 p7 “Aircraft Data Network” ES1 ES3 NS1 NS2 ES2 ES4 Network Switch End System • Full-Duplex Ethernet-based data network for safety-critical applications

  5. ARINC 664 p7 “Aircraft Data Network” ES1 ES3 NS1 NS2 ES2 ES4 RAM CPU NIC ROM

  6. ARINC 664 p7 “Aircraft Data Network” NS1 to ES1 ES1 ES3 NS1 NS2 ES1to NS1 ES2 ES4 dataflow link

  7. ARINC 664 p7 “Aircraft Data Network” ES1 ES3 τ1 τ2 τ5 vl2 NS1 NS2 ES2 ES4 vl1 τ4 τ3 virtual link • Highly critical application A1:τ1,τ2 andτ3 • τ1 sends message m1 toτ2 andτ3 • Non-critical application A 2:τ4 andτ5 • τ4sends message m2 to τ5

  8. ARINC 664 p7 “Aircraft Data Network” ES1 ES3 dp1 τ1 τ2 τ5 l1 l3 NS1 NS2 l2 l4 ES2 ES4 dp2 vl1 τ4 τ3 dataflow path • Highly critical application A1:τ1,τ2 andτ3 • τ1 sends message m1 toτ2 andτ3 • Non-critical application A 2:τ4 andτ5 • τ4sends message m2 to τ5

  9. ARINC 664 p7 “Aircraft Data Network” • Deterministic Event Triggered communication • Separation of traffic enforced through “bandwidth allocation” • Bandwidth Allocation Gap (BAG) – minimum time interval between two consecutive instances of a frame on a virtual link BAGx fx,1 fx,2 • Maximum bandwidth assigned to virtual link vli • BW (vli) = fi .size/BAGi

  10. TTEthernet • ARINC 664p7 compliant • Traffic classes: • synchronized communication • Time Triggered (TT) • unsynchronized communication • Rate Constrained (RC) – ARINC 664p7 traffic class • Best Effort (BE) – no timing guarantees • Standardized as SAE AS 6802 • Marketed by TTTechComputertechnikAG • Implemented by Honeywell on the NASA Orion Constellation

  11. TTEthernet • Composed of clusters • Each cluster has a clock synchronization domain • Inter-cluster communication using RC traffic ES5 ES7 ES1 ES3 NS2 NS1 ES2 ES8 ES4 ES6 • Cluster 2 • Cluster 1

  12. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT

  13. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  14. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  15. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  16. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  17. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  18. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  19. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  20. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  21. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  22. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  23. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  24. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  25. TT Transmission CPU P1,1 P2,1 B2,Rx τ1 τ4 B1,Rx B1,Tx P1,2 P2,2 B1,Tx τ3 τ2 B2,Tx B2,Tx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 CPU l k m FU FU f h TT e TTS TTR d b i b TTS a j g f2 P1,3 c f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m2 into frame f2 TTR checks if f2 arrives according to schedule a h Place f2 in buffer B1,Tx for transmission Place f2 in buffer B1,Tx for transmission b i Send time specified in send schedule SS Send time specified in send schedule SS c j TTS sends f2 to NS1 FU checks f2 d k f2 is sent on the dataflow link to NS1 Store the frame into receive buffer B2,Rx e l The Filtering Unit (FU) checks the frame f2 Task τ4 reads f2 from buffer f m Expected receive time specified in receive schedule SR g

  26. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  27. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  28. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  29. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  30. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  31. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  32. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  33. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  34. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  35. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  36. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  37. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  38. RC Transmission QTx CPU Q1,Tx P1,1 P2,1 B2,Rx τ1 τ4 Q2,Tx B1,Rx B1,Tx P1,2 P2,2 B1,Tx Q2,Rx τ3 τ2 B2,Tx B2,Tx Q1,Rx P2,3 SS SR SS NS2 NS3 ES1 NS1 ES2 8 9 f1 2 3 TP CPU RC 11 4 TR1 7 FU FU RCS 6 1 TR2 10 TT 5 TTS TTR 12 13 TTS f2 P1,3 f3 A1: τ1 àm1àτ3, RC f4 A2: τ2 àm2àτ4, TT Packing message m1 into frame f1 Traffic Policing (TP) checks that f2 arrives according to the BAG 1 8 Insert it in queue Q1,Tx 2 Traffic Regulator (TR) ensures bandwidth for each VL Copy f1 to outgoing queue QTx 3 9 RC scheduler RCmultiplexes frames coming from TRs Send f1 when there is no TT traffic 4 10 TTS transmits f1 when there is no TT traffic FU checks f1 5 11 Copy to receiving Q2,Rx f1is sent on the dataflow link to NS1 6 12 FU checks the validity of the frame Task τ3reads f1from the queue 7 13

  39. Problem formulation • Given • The topology of the network G • The set of TT and RC frames FTT and FRC • The set of virtual links VL • The assignment of frames to virtual links M • For each frame the size, the deadline and the period

  40. Problem formulation • Given • The topology of the network G • The set of TT and RC frames FTT and FRC • The set of virtual links VL • The assignment of frames to virtual links M • For each frame the size, the deadline and the period • Determine • The set of TT schedules

  41. Problem formulation • Given • The topology of the network G • The set of TT and RC frames FTT and FRC • The set of virtual links VL • The assignment of frames to virtual links M • For each frame the size, the deadline and the period • Determine • The set of TT schedules • Such that • The deadlines for the TT and RC frames are satisfied • The end-to-end delay of RC frames is minimized

  42. Motivational Example vl1 ES1 vl2 NS1 ES3 ES2 vl3

  43. Motivational Example • Initial TT schedule vl1 ES1 vl2 NS1 ES3 ES2 vl3

  44. Motivational Example • Optimized TT schedule vl1 ES1 vl2 NS1 ES3 ES2 vl3

  45. Optimization Strategy • TTEthernet Schedule Optimization (TTESO) strategy: • Tabu Search meta-heuristic • The TT schedules S • Such that: • TT and RC frames are schedulable • The end-to-end delay of the RC frames is minimized • Tabu Search • Minimizes the cost function • Explores the solution space using design transformations

  46. Optimization Strategy • Degree of schedulability • Captures the difference between the worst-case delay and deadline • Cost Function

  47. Optimization Strategy: Design Transformations • TT frame moves • advance frame transmission time • advance frame predecessors transmission time • postpone frame transmission time • postpone frame successors transmission time • RC frame moves • reserve space for RC frame • resize reserved space for RC frame • remove reserved space for RC frame

  48. Frame Representation for Moves ES1 ES3 NS1 NS2 ES2 ES4 vl1 [ES1, NS1] [NS1, NS2] [NS1, NS2] [NS1, NS2] f1,1 f1,1 f1,1 f1,1

  49. Design transformations: Postpone move

  50. Design transformations: Advance move

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