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系統程式

系統程式. Background. SIC Machine Architecture. Memory 8-bit bytes A word consists of three bytes and is addressed by the lowest numbered byte. A total of 32,768 ( ) bytes in memory Registers Five 24-bit special-purpose registers

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系統程式

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  1. 系統程式 Background

  2. SIC Machine Architecture • Memory • 8-bit bytes • A word consists of three bytes and is addressed by the lowest numbered byte. • A total of 32,768 () bytes in memory • Registers • Five 24-bit special-purpose registers • A (accumulator), X (index), L (linkage), PC (program counter), SW (status word) Note: PC, also called the instruction pointer (IP) in x86

  3. SIC (2) • Data Formats • 24-bit integers (no floating-point numbers) • negative values are represented by 2’s complement • 8-bit ASCII for characters • Instruction Formats 8 1 15 opcode x address

  4. SIC (3) • Addressing Modes • Direct Mode: x=0; TA=address • Indexed Mode: x=1; TA=address+(X) • Instruction Set • Load and store registers • Integer arithmetic • Value comparison • Branching if ((a>b) && (x<y)) c=a+b; else c=20+y-x; int a[10] for (int i=0; i<10; i++) a[i] = i;

  5. 存取指令：LDA Memory CPU A暫存器

  6. 存取指令：STA Memory CPU A暫存器

  7. 資料複製：LDA & STA Memory CPU A暫存器 C1=D1 LDA D1 STA C1

  8. 算術運算：ADD、SUB、MUL、DIV Memory CPU A暫存器 G1=R1+B1 LDA R1 ADD B1 STA G1

  9. LDA (LoaD into the register A) addr=0300 TA=0300 addr=0300 (X)=0100 TA=addr+(X)=0400 SIC Machine Instructions • Examples: • 000000000000001100000000 • 000000001000001100000000 (X)=0100 103000 0300 103333 0400

  10. 1 s 11 36 exponent fraction SIC/XE Machine Architecture • Memory: 1 MB • Register: Four new registers: B (base), S (general), T (general), F (floating-point accumulator) • Float-point • 48bits Data Format: n =

  11. 8 Discuss WHY 6 bits are sufficient. op 4 4 r2 r1 op 6 12 op x e disp i p n b 20 n p x i b e op address SIC/XE Instruction Formats • More complex instruction formats are required to meet the need to address 1MB. • SIC/XE has four instruction formats:

  12. SIC/XE Machine Instructions • Please refer to Figure 1.1 on page 11 • How does a SIC/XE processor • differentiate format 1, 2, 3, and 4 instructions? • differentiate format 3 and 4 instructions? • know when to compute target address using based relative addressing, program-counter relative address, or neither? • determine how to find actual operands with immediate, direct, indirect modes?

  13. Encoding Format Information OPCODE 0X 1X 2X 3X 4X 5X 6X 7X FORMAT 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 OPCODE 8X 9X AX BX CX DX EX FX FORMAT 3/4 2 2 2 1 3/4 3/4 1

  14. Decoding SIC/XE instructions • Suppose that you are given a machine instruction in the hexadecimal format. You decode the instruction with the following steps. • Determine the format of the instruction • (Rewrite the instruction in its binary format) • If it is a format 1 or 2 instruction… • If it is a format 3 or 4 instruction…

  15. Deciding SIC/XE Instruction Formats • Format 1: if first byte is CX or FX • Format 2: if first byte is 9X, AX, or BX • Format 3 or Format 4: all else • If n=i=0: a SIC instruction, get two more bytes • SIC/XE instructions all else • Decode the next byte and check the e bit • If e=0: Format 3 • If e=1: Format 4

  16. Decoding Format 1/2 Instruction • Format 1 • Find the opcode in Appendix A • Format 2 • Find the opcode in Appendix A • Translate register numbers back to corresponding register names • Tables on pages 5 and 7

  17. Decoding Format 3/4 Instructions • Steps: • Fill the rightmost two bits of the opcode with 0s • Find the opcode in Appendix A • If format 3 instruction, add 8 zeros (if binary format) or 2 zeros (if hexadecimal format) to the left of disp • Calculate target address according to bits x, b, and p • Determine the addressing mode according to bits n and i • Find the actual operand • Carry out the operation

  18. 解讀SIC/XE機器語言指令 找出Target Address

  19. TA = (PC) + disp Figure 1.1 TA = (PC) + disp = 3000+600=3600

  20. TA = (X)+(B) + disp Figure 1.1 TA = (X)+(B) + disp=90+6000+300=6390

  21. TA = (PC) + disp Figure 1.1 TA = (PC) + disp = 3000+30=3030

  22. TA = disp Figure 1.1 TA = disp = 30

  23. TA = disp Figure 1.1 TA = disp = 0C303

  24. Figure 1.1(Cont’d) The fifth example: 003600 0000 0000 0011 0110 0000 0000 According to the third paragraph on page 10, the b, p, and e bits merge with disp because n=i=0. Discussion: When would a SIC/XE assembler set n=i=0 and n=i=1?

  25. n=i=0 標記一個SIC指令 所以TA等於3600 Figure 1.1

  26. 解讀SIC/XE機器語言指令 找出實際運算對象

  27. TA是運算資料的位址 TA = (PC) + disp Figure 1.1 TA = (PC) + disp = 3000+600=3600

  28. TA是運算資料的位址 TA = (X)+(B) + disp Figure 1.1 TA = (X)+(B) + disp=90+6000+300=6390

  29. TA是運算資料的位址的位址 TA = (PC) + disp Figure 1.1 TA = (PC) + disp = 3000+30=3030

  30. TA本身就是運算資料 TA = disp Figure 1.1 TA = disp = 30

  31. SIC指令只要看x是否為1 n=i=0 標記一個SIC指令 所以TA等於3600 Figure 1.1

  32. TA是運算資料的位址 TA = disp Figure 1.1 TA = disp = 0C303

  33. SIC/XE機器語言指令的解讀 • 實際上，機器語言的解讀是非常機械化的過程 • 附錄A（第三版課本的第499頁上面）有更多的解讀機制 • 除了提供解讀更多機制之外，附錄A（第三版課本的第499頁上面）的表格，還揭露了SIC/XE CPU的設計有更多的限制。有一些看似可以的addressing mode並沒有出現在表格中。這一些是來自於硬體線路的設計的限制。對於SIC/XE來說，當然是假想的限制。

  34. 6 12 op x e disp i p n b SIC/XE (1) • e=1: format 4; e=0: format 3 • b=1, p=0: base relative TA=(B)+disp • b=0, p=1: pc relative TA=(PC)+disp (Negative values are in 2’s complement notation.) 20 op n i x p e address b n: indirect i: immediate x: index b: base p: program counter e: extended

  35. 6 12 op x e disp i p n b 20 n p x i b e op address SIC/XE (2) • b=0, p=0: simpleaddressing. (disp is used as the TA. For a Format 4 instruction, b and p are normally set to 0.) • i=1, n=0: immediate addressing • i=0, n=1: indirect addressing (Data addressed by TA is used as the address of the real operand.) n: indirect i: immediate x: index b: base p: program counter e: extended

  36. 6 12 op x e disp i p n b 20 n p x i b e op address SIC/XE (3) • i=n=0 or i=n=1: respectively, direct and simple addressing (TA is the location of the operand.) n: indirect i: immediate x: index b: base p: program counter e: extended

  37. SIC/XE (4) • Summary of addressing modes n i x b p e 0 Format 3 1 Format 4 1 0 0 Format 3, base relative 0 1 0 Format 3, pc relative 0 0 0/1 Format 3/4, disp is TA, direct 0 1 immediate (TA: operand) 1 0 indirect (TA: address of address) simple (TA: address of operand) 1 1 1 index

  38. SIC Programming

  39. ?????? ALPHA 000005 FIVE 5A CHARZ ?? C1 Figure 1.2 A register of SIC LDA FIVE STA ALPHA LDCH CHARZ STCH C1 ……… ALPHA RESW 1 FIVE WORD 5 CHARZ BYTE C’Z’ C1 RESB 1

  40. A = ALPHA A = ALPHA+INCR 000001 ONE ?????? ALPHA ?????? BETA ?????? GAMMA ?????? DELTA ?????? INCR Figure 1.3 A = ALPHA+INCR-1 A register of SIC LDA ALPHA ADD INCR SUB ONE STA BETA ……… ONE WORD 1 ……… ALPHA RESW 1 BETA RESW 1 GAMMA RESW 1 DELTA RESW 1 INCR RESW 1

  41. X(X)+1; (X):(ELEVEN) STATUS WORD, CONDITION CODE X Figure 1.4 A register of SIC STR2 STR1 ? T X register of SIC ? E ? S LDX ZERO MOVECH LDCH STR1,X STCH STR2,X TIX ELEVEN JLT MOVECH ……… STR1 BYTE C’TEST STRING’ STR2 RESB 11 ……… ZERO WORD 0 ELEVEN WORD 11 ? T ? ? S ? T ? R ? I ? N ? G ZERO 000000 00000B ELEVEN

  42. SIC Programming Examples • Figure 1.2 on page 13 • Figure 1.3 on page 15 • Figure 1.4 on page 16 • Figure 1.5 on page 17 • Figure 1.6 on page 19 • Figure 1.7 on page 20

  43. RESW: REServe Word RESB: REServe Byte Figure 1.2 int ALPHA; int FIVE=5; ALPHA=FIVE; CHAR CHARZ=‘Z’; CHAR C1; C1 = CHARZ; Format 1-8 label 9 blank 10-15 instruction 16-17 blank 18-35 operand 36-66 comments K1 WORD 1000 CHARS BYTE C’ABCDE’

  44. Figure 1.3 int ALPHA; int BETA; int GAMMA; int DELTA; int INCR; BETA=ALPHA+INCR-1 DELTA=GAMMA+INCR-1

  45. Figure 1.4 char str1[11]=“TEST STRING”, str2[11]; for (i=0; i<11; i++) str2[i]=str1[i];

  46. THREE WORD 3 Figure 1.5 int i, alpha[100], beta[100], gamma[100]; for (i=0; i<99; i++) gamma[i] = alpha[i]+beta[i];

  47. Figure 1.6

  48. 要記住回來的位址 L(PC); PCm 回到剛剛記住的返回位址 PC(L) Figure 1.7 Fetch-Decode-Execute

  49. Gains by Using SIC/XE • (Usually) smaller programs • (Usually) more efficient programs • Why?

  50. 假設記憶體存取費時n秒鐘 假設暫存器存取費時m秒鐘 Figure 1.2 LDA：2n 載入指令費時n秒鐘 載入資料再費時n秒鐘 STA：2n 載入指令費時n秒鐘 儲存資料再費時n秒鐘 合計2n+2n+2n+2n=8n秒鐘 LDA：n 載入指令費時n秒鐘 STA：2n 載入指令費時n秒鐘 儲存資料再費時n秒鐘 合計n+2n+n+2n=6n秒鐘

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