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A Versatile Technique for Linearly Tunable Transconductors

This paper presents a versatile technique for linearly tunable transconductors utilizing a master-slave configuration. This method enables linear tuning of input transconductance while maintaining stability across process, voltage, and temperature (PVT) variations. The proposed structure enhances circuit simplicity and ensures minimal dependency on bias conditions and process variations, addressing conventional drawbacks. Simulations based on standard 0.18µm CMOS technology demonstrate a wide tuning range and maintain linearity with a worst-case error of just 3%.

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A Versatile Technique for Linearly Tunable Transconductors

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  1. A Versatile Technique for Linearly TunableTransconductors George Raikos and SpyridonVlassis Electronics Laboratory Physics Department University of Patras http://www.ellab.physics.upatras.gr

  2. Introduction • Based on master-slave approach • Advantages : • Linear tuning of input transconductance • Wide tuning range • Stability over PVT corners • Circuit simplicity

  3. Principle of operation • Master transconductor: • Slave transconductor:

  4. Conventional differential pair • Disadvantages : • Dependency on process/temperature variations • Dependency on bias conditions • Inability for linear transconductance tuning

  5. Proposed structure • Cooperates master and slave diff. pair • Node k  IR–ITUNE • IR=Itune (due to negative feedback loop) • VR=50 mV • VCM=900 mV

  6. Proposed structure • Master transconductor : • Slave transconductor: • VR=50 mV • VCM=900 mV

  7. Proposed structure • Thus for slave transconductor: • is linearly tuned • is independent of process, temperature and supply voltage variations • (W/L)d.p.=20μm/0.3μm • VR=50 mV • VCM=900 mV • m=5

  8. Voltage generator • Provides VCM+1/2 VR and VCM-1/2 VR • Benefits : • Master and slave diff. pair share the same input common mode voltage • Master tracks the bias conditions of slave diff. pair • RG=2.5kΩ • R=1kΩ • C=1pF

  9. Simulations Results • Technology : standard 0.18um CMOS • VDD =1.8V • Simulation tools : • Monte Carlo tool • PVT corners tool

  10. Simulations Results • gm,in,slave – ITUNE for PVT corners • Worst case (PVT) for gm,in,slave was 3.5% • Linear tuning of gm,in,slave • Worst case (PVT) linearity error 3% for ITUNE 0.1μΑto 10μΑ

  11. Process, Supply, Temperature Corners

  12. Mismatches analysis

  13. Noise analysis (*) Without the proposed technique

  14. Conclusions • A versatile technique for linearly tunabletranscoductors was introduced • The input gm controlled through a DC current • Advantages : • Linear tunability of input gm • Wide range of tuning • Stability over process/temperature/voltage supply variations • Circuit simplicity

  15. Thank You For Your Attention!!!

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