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Chapitre 4 ATPG Algorithm

Chapitre 4 ATPG Algorithm. Alberto Bosio bosio@lirmm.fr http://www2.lirmm.fr/~bosio/ERII4_TEST/. 1. TPG. Reduced Fault List. Circuit description. Fault Selector. Fault Simulator. TPG Algorithm. Fault Coverage. Test Pattern. Target Fault. Detected Faults. TPG. Reduced Fault List.

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Chapitre 4 ATPG Algorithm

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  1. Chapitre 4ATPG Algorithm Alberto Bosio bosio@lirmm.fr http://www2.lirmm.fr/~bosio/ERII4_TEST/ 1

  2. TPG Reduced Fault List Circuit description Fault Selector Fault Simulator TPG Algorithm Fault Coverage Test Pattern Target Fault Detected Faults

  3. TPG Reduced Fault List Circuit description Fault Selector Fault Simulator TPG Algorithm Fault Coverage Test Pattern Target Fault Detected Faults

  4. Goals • ATPG: Automatic test pattern generation • Given • A circuit (usually at gate-level) • A fault model (for example stuck-at) • Find • A set of input vectors to detect all modeled faults. • Core problem: Find a test vector for a given fault. • Combine the “core solution” with a fault simulator into an ATPG system. The lecture has been taken from Prof. Agrawal VLSI test course (http://www.eng.auburn.edu/~agrawvd/COURSE/E7250_06/course.html) 4

  5. What is a test? Fault activation Fault effect X 1 0 0 1 0 1 X X Combinational circuit 1/0 1/0 Primary inputs (PI) Primary outputs (PO) Path sensitization Stuck-at-0 fault

  6. ATPG is a Search Problem • Search the input vector space for a test: • Initialize all signals to unknown (X) state – complete vector space is the playing field • Activate the given fault and sensitize a path to a PO – narrow down to one or more tests Vector Space Vector Space Circuit Circuit X X X X 0 1 0/1 sa1 sa1 001 101 6

  7. Need to Deal With Two Copies of the Circuit Good circuit X X 0 1 Alternatively, use a multi-valued algebra of signal values for both good and faulty circuits. 0 Same input Different outputs Circuit Faulty circuit X X 0 1 X X 0 1 0/1 sa1 1 sa1 7

  8. Multiple-Valued Algebras Fault-free circuit 1 0 0 1 X 0 1 X X Alternative Representation 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Symbol D D 0 1 X G0 G1 F0 F1 Faulty Circuit 0 1 0 1 X X X 0 1 Roth’s Algebra Muth’s Additions

  9. Example D D D D D D D 1/0 0/1 a b 1 c Input b 9

  10. D-Algorithm(Roth et al., 1967, D-alg II) • Use D-algebra • Activate fault • Place a D or D at fault site • Do justification, forward implication and consistency check for all signals • Repeatedly propagate D-chain toward POs through a gate • Do justification, forward implication and consistency check for all signals • Backtrack if • A conflict occurs, or • D-frontier becomes a null set • Stop when • D or D at a PO, i.e., test found, or • If search exhausted without a test, then no test possible 10

  11. Definition • Justification: Changing inputs of a gate if the present input values do not justify the output value. • Forward implication: Determination of the gate output value, which is X, according to the input values. • Consistency check: Verifying that the gate output is justifiable from the values of inputs, which may have changed since the output was determined. • D-frontier: Set of gates whose inputs have a D or D, and the output is X. 11

  12. Definition: Singular Cover • A singular cover defines the least restrictive inputs for a deterministic output value. • Used for: • Line justification: determine gate inputs for specified output. • Forward implication: determine gate output. X X a b 0 c Examples: XX0 ∩ 110 = 110 0XX ∩ 0X1 = 0X1 12

  13. Definition: D-Cubes D D D D D D D D D • D-cubes are singular covers with five-valued signals • Used for D-drive (propagation of D through gates) and forward implication X D a b X c Examples: XDX ∩ 1DD = 1DD 0DX ∩ 0D1 = 0D1 DDX ∩ DD1 = DD1 13

  14. D-Intersection D D D D D Undefined State (conflict) 14

  15. An Example c2 a2 a1 c c1 d e a b f b1 b2 Find tests for: c sa0 c1 sa0 c2 sa0 15

  16. Test for c sa0 a2 a1 d e c1 c a b b1 b2 f c2 • Action Operation D-frontier • Activate faultc=1 or c=c1=c2=D d, e • Justify c=1 XX1 ∩ 0X1 = 0X1, a=a1=a2=0 d, e • Forward impl a2=0 0DX ∩ 0D1= 0D1, d=1 e • Forward imp d=1 1XX ∩ XXX= 1XX , no implication possible e • D-drive c2→e DXX ∩ D1D= D1D, b2=b=b1=1, e=D f • Forward impl b1=1 011 ∩ 0X1 = 011, consistency checked f • D-drive e→f 1DX ∩ 1DD = 1DD, f=D PO • Stop, test foundTest: (a,b) = (0, 1), f = 1 16

  17. Test for c1 sa0 a2 a1 d e c1 c a b b1 b2 f c2 • Action Operation D-frontier • Activate fault c1=1 or c=c2=1, c1=D d • Justify c=1 XX1 ∩ 0X1 = 0X1, a=a1=a2=0 d • Forward impl a2=0 0DX ∩ 0D1= 0D1, d=1null • Back-up, redo step 3 No choice availablenull • Back-up, redo step 2 XX1 ∩ X01 = X01, b=b1=b2=0, a=X, d=X d • Forward impl b2=0 10X ∩ X01 = 101, e=1 d • Forward impl e=1 X1X ∩ XXX = X1X, no implication possible d • D-drive c1→d XDX ∩ 1DD= 1DD, a2=a=a1=1,d=D f • Forward impl a1=1 101 ∩ X01 = 101, consistency checked f • Forward impl d=D D1X ∩ D1D = D1D, f=D PO • Stop, test foundTest: (a,b) = (1, 0), f = 1 17

  18. Exemple (test for f3) f1 f2 A B f3 f4 C S f5 f6 f7 D f8 Collage à 1 E Collage à 0

  19. Sequential Circuits • A sequential circuit has memory in addition to combinational logic. • Test for a fault in a sequential circuit is a sequence of vectors, which • Initializes the circuit to a known state • Activates the fault, and • Propagates the fault effect to a primary output • Methods of sequential circuit ATPG • Time-frame expansion methods • Simulation-based methods

  20. Concept of Time-Frames • If the test sequence for a single stuck-at fault contains n vectors, • Replicate combinational logic block n times • Place fault in each block • Generate a test for the multiple stuck-at fault using combinational ATPG Vector – 1 Vector 0 Fault Unknown or given Init. state Time- Frame - n+1 Time- frame 0 Time- frame -1 Next state State variables Comb. block PO – 1 PO 0 PO – n +1

  21. Complexity of ATPG • Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: • Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. • Cyclic circuit – Contains feedback among flip-flops: May need SNff time-frames, where Nff is the number of flip-flops and S is the number of Symbols (i.e., 5 or 9) • Asynchronous circuit – Higher complexity! Time- Frame max-1 Time- Frame max-2 Time- Frame -2 Time- Frame -1 Time- Frame 0 Smax S2 S1 S0 S3 max = Number of distinct vectors with 9-valued elements= 9Nff

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