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Activities on tracker and calorimetry of Korean physicists

Activities on tracker and calorimetry of Korean physicists. The 2nd KILC Workshop, Pohang 2004/12/28. Silicon Tracker Silicon-Tungsten Calorimeter Tile-Tungsten Calorimeter. Youngdo Oh Kyungpook National University. ▣ Intermediate Tracker Configuration.

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Activities on tracker and calorimetry of Korean physicists

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  1. Activities on tracker and calorimetry of Korean physicists The 2nd KILC Workshop, Pohang 2004/12/28 • Silicon Tracker • Silicon-Tungsten Calorimeter • Tile-Tungsten Calorimeter Youngdo Oh Kyungpook National University

  2. ▣ Intermediate Tracker Configuration • stand-alone tracking capability • 5 layers at r = 9 to 37 cm • angular coverage |cosΘ|<0.9 • spatial resolution σ = 10 μm • thickness of a layer: 0.6% Xo Huge detector concept: TPC: Rmin = 40 cm Do not expect much changes in IT

  3. Intermediate Tracker Designfor GLC- Double-sided silicon microstrip detectors i. excellent spatial resolution ii. well-established technologyLayout of the IT surrounding the VTX.- The distance between the last layer of VTX and the first layer of Trackeris about 39cm in Large detector design.i. 5 layers of coaxial cylinders at 9, 16, 23, 30 and 37cmii. covers | cosΘ |<0.90 coinciding with the region covered by VTX

  4. IntermediateTracker R&D Activities in Korea √linking and reconstruction efficiency (Fast Simulation) √ track momentum resolution (Full Simulation) √ DSSD simulation/design/fabrication Electronics(RC chip, VA1TA, FADC), DAQ √S/N ratio measurement and beam test Sensor - Kyungpook National University - Korea University - Seoul National University - Chunnam National University - Sungkyunkwan University

  5. ▣ MASK Design : P Side 64ch 100um pitch sensor 512ch 100um pitch sensor Without hour glass 1cm PIN Diode 16ch 100um pitch sensor 32ch 100um pitch sensor For SDD R&D PIN Diode array 512ch 100um pitch sensor With hour glass 16ch 100um pitch SSD

  6. n+ ohmic side 1st metal p+ junction side 2nd metal readout line Metal 1 and metal 2 contact (VIA) ▣ Silicon sensor R&D <- Details by B.G.Cheon • • double sided silicon strip • • tree metal process • implant strips in ohmic • side are orthogonal to • those in junction side • readout strips in junction • side have the same • direction as that of ohmic • side Front Side: - brown: implanted n+ - blue: p-stop - sky blue: SiO2 - gray: Al for readout Back Side: - blue: implanted p+ - first gray: 1st metal - sky blue: SiO2 - vertical gray: VIA - second gray: 2nd metal

  7. p+ implanted readout strip n+ implanted readout pad in staggering via in hourglass p-stop in atoll guard ring N side P side ▣Silicon Sensor

  8. ▣Measurements

  9. ▣Measurements of the sensor These are disappeared after insulating wafer edges

  10. Silicon-Tungsten Calorimetry Why Silicon for Calorimeter? • Advantage well known, well proven technology, proven high accuracy • High granularity, but expensive to date • Built-in ShowerMax & Presampler • Modest Tracking capability for both charged/neutral particles • Sampling EM and even Hadron calorimeter • Cost • At moment 10 times more expensive that other types, but will be comparable in next 5 years • Cost depends on how you build it • Many grounds do R&D

  11. Pixels(Signal) Guard Ring SiO2 p+ 650㎛ N-type silicon 5 ㏀ Al Korean Silicon Sensor (1st Prototype, Oct.2002) • DC coupled • 4*4 array matrix in 4 inch wafer • Pixel size : 1.5 * 1.4 cm^2 • 3 guard rings

  12. Korean Silicon Sensor (Mass Production in 2003-4) 20um 60um Clean wafer gap between sensors Oxidation N+Diffusion Cover with photoresist Expose through mask Develop Etch, Stip P+ImplantationAnneal Metallization Fab at SENS Technology (www.senstechnology.co.kr) • Fabricated a sensor on 5’ wafer using the method of “stepper” • Size : 6.52*5.82 cm2 (including 3 guard rings ) • array : 4*4 matrix • Pixel size: 1.55 * 1.37 cm2 • Full depletion voltage : 90V • Leakage current level : about 3 nA per pixel at full depletion voltage 3 Guard Rings CALICE : 6*6 pixels, each 1cm*1cm (4” wafer) 525um or 380um thick Fabrication process

  13. Capacitance Measurement Full depletion voltage : 90V

  14. Dark box sensor Photodiode Pb Pb Beta (90Sr) source S/N Ratio Measurement with Sr-90 source(use of single channel very low noise preamp) Trigger Photodiode Discriminator GateGenerator ShapingAMP S/N ~ 120 PreAmp PreAmp for sensor

  15. ACP Board FPGA Power DC Voltage High Voltage ADC Digital Electronics : ADC, Contorl, Power Board • ADC: MAX 1133 • Sampling Speed : 200ksps • (200ksps X 16bit = 0.4Mbyte/s) • Resolution : 16bit (65536 Level)

  16. Tungsten • size : 65.5 mm X 57.5 mm ( ~ sensor size) • thickness : 3.5 mm (= 1 X0) • purity : close to 99% (Rm = 9mm) tungsten

  17. CERN Beam test ( 2004/8~9) Layers of Si sensors and Tungstens Digital readout boards and PC interface Frontend readout boards Beam Direction

  18. Data Summary (50GB) Beam Beam Energy (GeV) files Etc 4x4x20 Muon 150 23 TD Check Electron 50 33 TD Check Pion 150 35 Sensor scan 4x4x20 Tungsten Pion 150 12 Muon 150 42 Electron 150,100, 80,50, 30 ,20 ,10 399/37~89 3 4x8x10 Tungsten Pion 150 Muon 150 18 Electron 150, 100, 50, 20 162/36~48

  19. Detector Response to Electron Beam(sum of all channel) First look of data 150 GeV Electron 100 GeV Electron 80 GeV Electron 50 GeV Electron 30 GeV Electron 20 GeV Electron 10 GeV Electron Total ADC of an event / 640

  20. Energy Resolution vs Energy First look of data Very preliminary dE / E (%) Analysis is underway Electron Energy in GeV

  21. Tile-Tungsten Calorimeter

  22. Wolfram Scintillator Tile Tungsten Calorimeter R&D • Prototype Layout One Layer : Wolfram 20cm X 20cm X 0.3cm Scintillator 1cm X 20cm X 0.2cm X 20  Total: 30 Layers

  23. Current Status • Survey almost finished for the all the components • aimed all the components supplied in Korea • Largely five components Tungsten, Scintillator, SiPM, Simulation package, readout electronics • R & D has already been started for some parts • expect very active R & D for the next two years • 3 professors from Kobe, Shinshu and Niigata universities visited KNU • on Dec 7 – 9 to discuss the cowork about TiCAL • - development of SiPM • - Readout • - Scintillator • - Physics simulation using current simulation tools, ( Mokka, Jupiter ..)

  24. Tungsten • TaeguTec(전 대한중석회사)에서의 텅스텐 판 제작 가능성 타진 • 판 구조의 가능성 : Alloy, Heavy metal or other ??? • W:Ni:Cu=95:3.5:1.5 Alloy • WC + Cr heavy metal • W:Pb = 7:3 ??? : new possibility • 현재 100 mm by 100 mm 판 제작 가능. • 성분 구성에 대한 모의시늉 등 연구 필요 • W와 Pb 구성이면 매우 만들기 쉬움 –모의시늉 필요 • 회사측과 연구/개발 협의

  25. SiPM • 한국/러시아/일본 공동연구 수행. • Quantum Efficiency 향상 • Noise level의 줄임 • 국내에서의 제작

  26. Scintillator • 1 cm 정도 폭의 strip 형태의 scintillator는 필연적임. • 압출 기술에 의한 scintillator 제작 • Fermilab 팀과 연구/개발하기로 합의 • Light yield를 높이기 위한 성분 시험 • Groove 디자인 등등 • 모든 scintillator의 제작 한국에서 가능

  27. Simulation • Geant4 based Simulation packages are considered. : Mokka, Jupiter • Mokka : installed - running successfully - geometry database installed at KNU - We are ready to open account to anyone interested in running physics. • Jupiter : not yet - Japanese site doesn’t distribute official version yet - We asked cooperation when Japanese professors visited KNU - And we are also asked to cowork about physics simulations. • As first stage, we are interested in physics simulation of SUSY using susygen3.0 and SUSY parameter scan.

  28. Summary • Silicon tracker and silicon sensors are fabricated at Korea. • Sensor R&D is underway. • First Prototype of silicon calorimeter was tested at • CERN. • Started design optimization and R&D work of TiCAL proto type • R&D of Scintillator, W, SiPM • R&D of Readout Electronics • Ready for physics simulation •  need informations and discusstions with • theory & physics working group • Target : Prototype beam test at Fermilab (summer, 2006)

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