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Updates on BCC Hardware Testing and Serial Powering Developments

This document provides a summary of recent activities and developments regarding the BCC (Beam Conditioner Controller) hardware and associated testing, as discussed during the stave meeting on December 10, 2010. Key topics include noise measurements, segmenting serial power in chains, assembly updates, and various action items for upcoming meetings. Additionally, it highlights the current status of the BCC V3 fabrication, firmware details, and the power supply configurations for BCC boards. The importance of measuring amplitude margins and clock bus resistance is also emphasized.

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Updates on BCC Hardware Testing and Serial Powering Developments

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Presentation Transcript

  1. Intro & BCC-HSIO Status Carl Haber Dec 10, 2010 Stave Mtg

  2. Intro and News • Some action items for AUW • DC-DC stavelet • Noise measurements on 1st stavelet • Ground bounce – how should serial power be segmented on a chain-of-24? • Distribution of module assy hardware • Working meeting: Feb 1-2 RAL • New IT-SC: pixel-strip overlap

  3. Hardware • HSIO has been distributed • Interface boards have been sent to UK (10), CERN (6), BNL • 15 End-of-Stave are now in assembly • BCC V3 is in fabrication • Will produce and test new BCC boards for these

  4. Chain of 24 BCC Tests

  5. Powering Serial power board Loopback board BCC board

  6. Configuration • BCO out from BCC is LVDS and is locally terminated in 100 W • BCO in is driven from the EOS card, line is terminated in 60 W and back terminated in 100 W. Driver is M-LVDS • Expected line impedance is ~70 ohms (4-4-4-6 mil) • EOS driven from HSIO and new interface card • Firmware drives a 40 MHz BCO clock • BCO input network is 1M-10K-1M • BCC can be powered parallel (2.5 V, 1.08 A for 24) • BCC can be powered in series 24*2.5 V, 50 mA

  7. With attenuation on the clock bus, the input offset was too high with this nominal network (150 mV) • Switch to 1M-10K-1M (12 mV offset) • BCO out duty cycle is now solid at 50%

  8. BCO in vs Position

  9. Duty Cycle is 50% @ all Pos’n

  10. BCO input amplitude vs pos’n Amplitude is measured both with scope peak to peak function (blue) and manually with cursor tool (red) Prediction from Chain-of-8 This attenuation is due to series resistance down the clock bus, not clear why it flattens out around the mid-point (lithography?)

  11. Issues from AUW • It would be nice to know how much amplitude margin we have before duty cycle can become an effect again • Compare performance with serial powering • Measure 80 MHz DCLK asymmetry on 24 BCC • Measure resistance down clock bus • Vary end and back termination (?) • Check BCO out for BCO off – chatter • Find IDELAY settings for 24 data outs • EOS Tester code is being extended from 8 to 24

  12. DCLK pattern for 24 BCC

  13. DCLK Pattern for 24 BCC Pattern is very regular for this sample of 24 BCC V2

  14. Serial Power • Serial regulator chain works DC for 1-24 drops when tested with a simple resistive load • Next step is to power 1,2,3….24 BCC in sequence: done, works OK • See correct DC response but BCC response is inconsistent for small number of loads • Due to unpowered load on bus, not an issue

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