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Huazhong Normal University (CCNU)

A Possible Proposal for TOF-MRPC readout electronics (based on CERN RD51 scalable readout system). Dong Wang. Huazhong Normal University (CCNU). Outline. Introduction to the Scalable Readout System MRPC Readout Specification Application of the SRS to CMB-MRPC Summary.

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Huazhong Normal University (CCNU)

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  1. A Possible Proposal for TOF-MRPC readout electronics (based on CERN RD51 scalable readout system) Dong Wang Huazhong Normal University (CCNU)

  2. Outline • Introduction to the Scalable Readout System • MRPC Readout Specification • Application of the SRS to CMB-MRPC • Summary

  3. ---Introduction to the Scalable Readout System Scalable Readout System from: https://espace.cern.ch/rd51-wg5/default.aspx

  4. ---Introduction to the Scalable Readout System scalable readout system characteristics • Links instead of buses: more reliable, longer distance, more bandwidth • Scalable: small system= few links 1SRU, large system= N links • Merge 3 streams :single DTC link (Data, Trigger, Control )copper or fiber • Chip frontend exchangeable: keep the common readout system • Cheap & standard: frontend card chassis (Eurocard format), cables(CAT6 cable) , fibers(850 nm MM fiber), network(10 Gigabit Ethernet) • DAQ system: robust, user-friendly and supported: Alice / DATE • Radiation protected on FEC and SRU FPGA chips from: https://espace.cern.ch/rd51-wg5/default.aspx

  5. ---Introduction to the Scalable Readout System from: https://espace.cern.ch/rd51-wg5/default.aspx

  6. ---MRPC Readout Specification The CBM-TOF wall Design requirements • Overall time resolution σT = 80 ps. • Occupancy < 5 % for Au-Au central collisions at E=25 GeV/A. • Space resolution ≤ 5 mm x 5 mm. • Efficiency > 95 %. • Pile-up < 5%. • Rate capability > 20 kHz/cm2. • Multi-hit capability (low cross-talk). • Compact and low consuming electronics (~65.000 electronic channels). The TOF wall of the CBM experiment at FAIR 15-03-2007 D. Gonzalez-Diaz (GSI-Darmstadt)

  7. ---MRPC Readout Specification Fast read out Data rate • One SRU can handle 2304 channels 1 SRU = 36 FEE = 36*8 TDC = 36 * 8*8 channel = 2304 channel • ~65000 CBM/TOF channels = ~30 SRU needed • One SRU-DROC link can support 6Gb/s data rate maximum • One FEC-SRU link can support 200Mb/s data rate via cat6 connection

  8. Architecture of the readout Chain from: https://espace.cern.ch/rd51-wg5/default.aspx

  9. ---Application of the SRS to CMB-MRPC SRU architecture TTC fiber (LHC) Power +3.3V, +4.2V, -12V JTAG FLASH Molex 87831-1420 TTCrx XCF32P-VOG48 DCS mezzanine MIC29301 MIC29301 Clock outputs +2.5V +3.3V RJ45 70 pin connector 70 pin connectors Con13 CON14 LT1175 RJ45 TPS74401 Ethernet-DCS DCS ethernet cable - 5V +1V AD7417 54 LVTTL bus signals ( 32 data 16 addr. 3 cntr. 1 Rst ) 8 TTC signals (4 Broadcast, 2 strobes, 2x clock ) 5 other (2 x ADC, 1 ext. Inp, 2 RxTx ) LDO area 67 I/O signals Gigabit Ethernet T+V monitoring PHYSICAL VIRTEX5 LXT NIM input 2x RJ45M 88E 1111 1000 BASE- T ( 1 GB copper) 35 I/O signals 4 I/O signals 2 Rocket I/O Optical SFP 10 GBASE-S (10 GB* optical) LVDS coax 4x bidir 4 x SN65LVDS100 25 MHz 125 MHz ICS844021 I-01 clock s 4 diff LVDS ( 8 I/O) 40 MHz 128 x differential LVDS (256 I/O) 128 x SN65LVDS100 . . . 32 x RJ45 . . . 32 x Serial quad LVDS links (CAT6) from: https://espace.cern.ch/rd51-wg5/default.aspx

  10. ---Application of the SRS to CMB-MRPC SRU board Prototype • First version of SRU board layout finalized. • First success with porting of DATE software to Gigabit Ethernet . from: https://espace.cern.ch/rd51-wg5/default.aspx

  11. from: https://espace.cern.ch/rd51-wg5/default.aspx

  12. ---Application of the SRS to CMB-MRPC MRPC electronic chain concept from ALICE/TOF

  13. ---Application of the SRS to CMB-MRPC Front-adapter card options A,B-cards C-cards A, B card: ~100x89 mm2 C-card: ~ 128x233 mm2 A cards : custom chip adapter, ADC’s etc B cards: options, Extensions (LEDs, HV bias etc.) C-cards: larger, more complex extensions Note: A,B and C cards can be mixed in single Eurocrate

  14. ---Application of the SRS to CMB-MRPC FEC card • A-card • 4 HPTDC chips FEC card • To be defined: • Connectors on A card to FEA • Power for FEA card • might also use larger C-card The analog electronic Part can be designed based on GSI/CBM group collaborate, ALICE/TOF NINO/HPTDC tecnology, or collaborate with other groups.

  15. Summary • CCNU is RD51 member • Adapter card design and firmware of FEC will be designed by CCNU • FEC card and DATE Readout will supported by RD51 • Connectivity to FEA to be studied • Existing ALICE readout system: DATE being ported to GBE • First version of SRU has finished design at CERN • Upgrade version of SRU is under development at CCNU

  16. Thank you!

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