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Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth

Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth

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Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth

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  1. Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth 2010 Technology Roadshow

  2. Agenda The need for bandwidth The challenge Introducing 28-nm Stratix V FPGAs andHardCopy V ASICs Key innovations and benefits Summary

  3. Expanding Bandwidth Demands Mobile InternetEstimated 1.7B users by end of 2013 Fiber to the Home Estimated ~130M connections by end of 2013 3G NetworksExpected to be 38% of worldwide market by end of 2013 LTE/WiMAX (4G) ~5.6M users expected by end of 2013 Cloud ComputingHosted mobile applications estimated to reach 998M users by 2014 Mobile BackhaulEstimated 90,000 Gbps of capacity required by end of 2013

  4. Market Dynamics for High-End Systems Mobile Internet driving bandwidth at 50% annualized growth rate Fixed footprints Existing power ceilings 40G/100G system deployment with 200G/400G on the horizon Communications Broadcast Military Computer & Storage • Worldwide proliferation of HD/1080p • Move to digital cinema and 4K2K • Fixed power budget • Heightened intelligence and defense needs • More sensors, higher precision driven to decision points faster • Power and uptime critical • Higher bandwidth, performance and lower latency • New interface standards with PCI Express Gen3 and QPI Demand for Higher Bandwidth in Same Footprint at Same or Lower Power and Cost

  5. Increasing Bandwidth with Strict Power and Cost Budgets Bandwidth Price/Power Time How to Increase Bandwidth, Without Increasing Cost or Power?

  6. TSMC’s High-Performance 28-nm Process • 28-nm process advantages • 2X the capacity • 35% higher performance than alternative process options • Analog performance advantages enable faster and more power efficient transceivers • Enables 30% lower total power • Altera’s patented process innovations address yield, performance, and power • Redundancy • Programmable Power Technology • Customized extra-low leakage devices • 17-year relationship, with joint development First to 40 nm, First to 28 nm

  7. Innovations to Address the Challenge Highest Integration Ultimate Flexibility Highest Bandwidth • 12.5-Gbps transceivers • 28-Gbps transceivers HardCopyBlock Enhanced Fabric with Partial Reconfiguration HardCopyBlock Stratix V FPGAs and HardCopy V ASICs: A New Class of Devices, Ready for the Challenge 28-nm high-performance process Embedded HardCopy Blocks Partial reconfiguration

  8. Stratix V FPGAs – Built for Bandwidth • Highest bandwidth • 66 transceivers capable of 12.5 Gbps and 7 x72 800-MHz DDR3 interfaces • Devices with 28-Gbps transceivers • Unprecedented level of integration • Embedded HardCopy Blocks supporting PCI Express Gen3 and 40G/100G Ethernet • High-performance, high-precision DSP • Enhanced logic fabric with 1,100K LEs, 53 Mb RAM, and 3,680 18x18 multipliers • Ultimate flexibility • Fine-grain and easy-to-use partial reconfiguration • Configuration via PCI Express • 50% higher system performance and 30% lower power Highest Bandwidth Hard IP and Flexibility IP Solutions and Ecosystem

  9. HardCopy V ASICs – Risk-Free Path to ASIC Risk-free path to lower cost and up to 50% lower power with HardCopy V ASIC Up to 2X core performance improvement One design, one IP set, one tool delivers both FPGA and ASIC implementations Low NRE, with fast and predictable turnaround times Guaranteed first-time right No-Risk Path to Volume Production Highest Bandwidth at Lowest Cost and Power

  10. Stratix V Device Family Variants Stratix V GT FPGA Optimized for applications requiring ultra-high bandwidth and performance with 12.5-Gbps and 28-Gbps transceivers Stratix V GX FPGA For high-performance, high-bandwidth applications with transceivers up to 12.5 Gbps Stratix V GS FPGA Optimized for ultra-high performance DSP, high-bandwidth applications with transceivers up to 12.5 Gbps Stratix V E FPGA For highest density, high-performance applications

  11. Stratix V High-Bandwidth Transceivers Up to 66 identical, continuous-range, low-power, backplane-capable transceivers running at 150 Mbps to 12.5 Gbps Devices with 28-Gbps transceivers Sub-picoseconds jitter for best eye opening and system BER performance Dynamic reconfiguration of transceiver settings On-die instrumentation – EyeQ eye viewer per transceiver channel 12.5- and 28-Gbps transceivers

  12. Stratix V FPGA On-Die Instrumentation View receiver signal margin with Altera’s EyeQ eye viewer Complete vertical/horizontal reconstruction of eye opening Engage in live debug while fine-tuning for ideal equalization EyeQ Pre-Emphasis EQ CDR Lossy Medium Rx Tx Minimize Board Bring-Up/Debug Time with Dynamic Reconfiguration and EyeQ

  13. Extending Transceiver Leadership 2X the transceiver bandwidth at the same power 50% lower power per transceiver channel 200 mW per 28-Gbps transceiver or ~7mW/Gb Transceiver PMA Power Per Channel Stratix V FPGAs 168 mW/Ch @ 12.5 Gbps - 50% from 40 nm 250 200 20 Power (mW) Per Channel (PMA) 15 150 mW Per Gigabit (Gb) 10 100 10 50 0 0 28 Gbps 6.5 Gbps 8.5 Gbps 10.3 Gbps 11.3 Gbps 12.5 Gbps Stratix V Transceivers:Highest Bandwidth and Power Efficiency

  14. Highest memory bandwidth with up to 7 x72 DDR3 DIMMs with multi-rank support Half the latency with the new UniPHY Hard I/O FIFOs and read/write paths High system reliability through duty cycle correction, calibration algorithms, and VT compensated deskew delays Sharing of PLLs and DLLs across multiple interfaces Guaranteed timing closure and focus on user productivity and ease of use Stratix V Memory and I/O Performance Delivering Highest Memory and I/O Performance and Bandwidth

  15. The New Embedded HardCopy Block • Used to harden standard or logic-intensive functions • Reduces system cost and faster time to market • Provides 2X performance enhancement • 3-6 months turn-around time for new variants to address targeted applications 14M ASIC Gates/700K LEs withup to 65% Lower Power than Soft Implementation

  16. Partial Reconfiguration in Stratix V FPGAs Partial Reconfiguration for the Core • Ultimate flexibility enabled by partial and dynamic reconfiguration • No system downtime with dynamic updates • Faster reconfiguration • Reduces cost and power through integration • Built on proven methodology using LogicLock™ and incremental compile A2 C2 A1 C1 B1 FPGA Core Transceivers Dynamic Reconfiguration for Transceivers F1 D1 E1 A2 C2 B1 FPGA Core Transceivers D1 E1 F1 #1 in Productivity and Performance

  17. Configuration Via PCI Express (CvPCIe) Initialize or update FPGA fabric via PCI Express (PCIe) Three steps for using CvPCIe Program the PCIe hard IP (HIP) via serial SPI flash device Program autonomous HIP before FPGA CvPCIe completes programming of FPGA Always meet PCIe link bring-up time < 100ms Lower cost by using cheaper configuration file memory Faster configuration and enhanced system flexibility Configure PCIe HIP Serial SPI Flash 4 pins Load FPGA Image via PCIe Link PCIe Hard IP Endpoint PCIe Link Gen1/2/3 x1, x2, x4, x8 Host PC

  18. Altera Leads the Way Again in Fabric Innovation • Enhanced adaptive logic module (ALM) with 4 registers • 5.5X more routing connections than competing devices • Enhanced embedded memory structure for more memory bits and ports with M20K • Faster MLAB blocks and support for wide shallow FIFOs • High-resolution clock synthesis with up to 32 fractional PLLs • More clock sources and networks with the ability to power down unused logic Higher Logic Efficiency and System Performance

  19. The Need for Variable Precision in DSP Addresses the key challenge of supporting multiple precision requirements of various systems DSP SYSTEM PRECISION 36x36 27x27 54x54 9x9 18x18 12x12 18x36 VIDEO WIRELESS, MEDICAL MILITARY, TEST, HP COMPUTING

  20. First Variable-Precision DSP Block • Additional features for more efficient implementation of DSP algorithms • 18-/26-bit pre-adder • Internal coefficient storage • 64-bit accumulator • 64-bit cascade bus 1 2 3 4

  21. Highest System Performance on 28 nm TSMC’s high-performance process 50% increase in memory interface performance 1.6-Tbps serial switching capability Enhanced core fabric 1,840 GMACS of signal-processing performance Embedded HardCopy Blocks for 2X performance vs. soft logic 800-MHz DDR3 DIMM 600-MHz Memory Blocks 12.5-/28-Gbps Serial Transceivers Embedded Hardcopy Blocks Up to 3,680 Variable-Precision DSP Blocks Enhanced ALM and Routing 50% Increase in System Performance

  22. Stratix V Technologies to Control Power 30% Lower Total Power

  23. A Complete Solution EmbeddedSoft-Core Processors SOPC Builder Advanced DSP Builder Intellectual Property Design Software

  24. Highest bandwidth with 12.5- and 28-Gbps transceivers Highest level of system integration through extensive hard IP integration and the new Embedded HardCopy Blocks 50% higher system performance at 30% lower total power Ultimate flexibility with easy-to-use partial reconfiguration Lowest risk path to HardCopy V ASICs Productivity advantage with Quartus II software system solutions, tools, and IP for vertical markets Stratix V FPGAs and HardCopy V ASICs Built for Bandwidth

  25. Learn More Download the white paper Introducing Innovations at 28 nm to Move Beyond Moore’s Law Download the Stratix V Device Handbook

  26. Thank You!For more information visit: