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Pyxis

Pyxis. April Lewis Aaron Martin Steve Sherk. Pyxis1600. General-purpose 16-bit RISC microprocessor 16 16-bit registers 16-bit address bus Up to 64KB of addressable memory. Registers. 16 registers 3 special purpose $r0 – zero $r14 – stack pointer $r15 – return address

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Pyxis

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  1. Pyxis April Lewis Aaron Martin Steve Sherk

  2. Pyxis1600 • General-purpose 16-bit RISC microprocessor • 16 16-bit registers • 16-bit address bus • Up to 64KB of addressable memory

  3. Registers • 16 registers • 3 special purpose • $r0 – zero • $r14 – stack pointer • $r15 – return address • 13 general purpose • $r1 - $r13 • Status register (sr) • 8 bits – carry (c), overflow (o), negative (n), zero (z), interrupt enable (i), less than (l), 2 bits unused • Program counter (pc) • Accumulator high (ah) and accumulator low (al) • Used for multiply and divide • Interrupt Return Address (IRA) • Register to hold return address from interrupt

  4. Instruction Formats 15 9 8 7 4 3 0 R-type • 16-bit instructions • 7-bit opcode • 1 bit to indicate information in next word • rd is source and target • rs is source • Branch instructions use special format opcode ext rd rs 15 0 Displacement / Immediate 15 13 12 9 8 0 B-type opcode branch type address

  5. Instruction Set

  6. Instruction Set Assembly to Machine Code Example add r3, r4; comp r10, r4; beq #25; jmpr r9; 0000001 0 0011 0100 1111111 1 1010 0100 1110000 x xxxx xxxx 0000 0000 0001 1001 010xxxx x 1001 0000

  7. Addressing Modes • Register direct • Register indirect plus displacement • Use r0 for absolute addressing • PC-relative • Immediate

  8. Datapath

  9. Control Signals

  10. Control Signals

  11. IRWrite=1 RegWrite=0 PCWrite=0 Arithmetic Instructions Write to Reg from ALU Load from Memory Write to Memory IorD=0 MemRead=1 MemWrite=0 IRWrite=0 ALUOp=ADD ALUSrcA=2 ALUSrcB=2 PCSrc=0 PCWrite=1 RegWrite=0 ALUSrcA=0 ALUSrcB=0 ALUOp=OP IRWrite=0 RegWrite=0 PCWrite=0 ALUSrcA=0 ALUSrcB=1 ALUOp=ADD IRWrite=0 RegWrite=0 PCWrite=0 RegWrite=1 MemtoReg=0 ALUOp=OFF IRWrite=0 PCWrite=0 ALUSrcA=1 ALUSrcB=0 ALUOp=OP IRWrite=0 RegWrite=0 PCWrite=0 IorD=1 MemWrite=1 ALUOp=OFF RegWrite=0 IRWrite=0 PCWrite=0 IorD=1 MemRead=1 ALUOp=OFF RegWrite=0 IRWrite=0 PCWrite=0 RegWrite=1 MemtoReg=1 ALUOp=OFF IRWrite=0 PCWrite=0 State Transition Diagram 0 Fetch 1 IorD=0 MemRead=1 MemWrite=0 ALUOp=ADD ALUSrcA=2 ALUSrcB=2 PCSrc=0 PCWrite=1 RegWrite=0 Decode R-type (ext=1) Fetch Immediate 4 R-type (ext=0) 2 Execute Calc EA Calc EA or Immediate 8 Write-back ALU to Reg 3 5 Memory Write Memory Read 9 6 To State 0 Write-back Mem to Reg 15 7 Check Interrupt

  12. IRWrite=1 RegWrite=0 PCWrite=0 IorD=0 MemRead=1 MemWrite=0 ALUOp=ADD ALUSrcA=2 ALUSrcB=2 PCSrc=0 PCWrite=1 RegWrite=0 RegWrite=1 MemtoReg=1 ALUOp=OFF IRWrite=0 PCWrite=0 ALUSrcA=0 ALUSrcB=0 ALUOp=SUB IRWrite=0 RegWrite=0 PCWrite=0 ALUSrcA=0 ALUSrcB=0 ALUOp=ADD PCSrc=0 PCWrite=1 IRWrite=0 RegWrite=0 ALUSrcA=2 ALUSrcB=3 ALUOp=ADD PCCond=1 PCSrc=0 PCWrite=1 IRWrite=0 RegWrite=0 PCSrc=1 PCWrite=1 IorD=0 MemRead=1 MemWrite=0 ALUOp=OFF RegWrite=0 IRWrite=0 Conditional Branch Jump to Register Address Jump to Register Address and Link Jump to Immediate and Link Jump to Immediate State Transition Diagram Fetch 0 1 Decode R-type Jump &Link R-type Jump (ext=1) R-type Jump (ext=0) B-type Save Return Addr 13 Jump to Reg Addr Compare 10 12 14 Jump 11 Update PC To State 15

  13. Interrupts • Interrupts will be checked at the completion of each instruction • An interrupt will trigger some extra states that send the processor to an Interrupt Service Routine (ISR), pre-programmed in code memory. • These states will perform the following: • Save the processor’s state • Disable interrupts • Jump to the ISR • The ‘RETI’ instruction will return the processor from the ISR

  14. Virtex XCV300 FPGA • XCV300 FPGA • - 322,970 logic gates • - 8 KB on-chip RAM • - Block SelectRAM • - Fast arithmetic carry • - Clock Speed 10MHZ • - Multiple I/O standards (LVTTL, LVCOMS2)

  15. Input / Output Serial Interface • UART Transmitter and Receiver Macros UART_TX UART_RX 8-bit Serial Serial 16 Byte FIFO BUFFER 8-bit 16 Byte FIFO BUFFER These macros are fully compatible with standard UART communications protocols such as to a PC, providing level shifting components are employed to generate RS232 signaling. The buffers will be interrupt driven.

  16. Memory Timing Diagrams • 32KB FLASH (AT29C256-70PC) Total access time is 70ns (tACC) 70ns

  17. Memory Timing Diagrams • 32KB SRAM (K6x0808C1D-DF70) Total access time is 70ns (tAA)

  18. 32KBx8 off-chip SRAM32KBx8 off-chip FLASH

  19. Parts List

  20. Roles and Responsibilities • Aaron • Logic design • Verilog programming • Hardware implementation • April • Logic design • Verilog programming • Assembler • Steve • Logic design • Verilog programming • Hardware implementation • All • Test programs • Integration and Test • Documentation

  21. Schedule

  22. Questions

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