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Lecture 8 Memory Elements and Clocking

Lecture 8 Memory Elements and Clocking. Hai Zhou ECE 303 Advanced Digital Design Spring 2002. Outline. Sequential logic networks Latches (RS Latch) Flip-flops (D and JK) Timing issues (setup and hold times) READING: Katz 6.1, 6.2, 6.3, Dewey 8.1, 8.2. Sequential Switching Networks.

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Lecture 8 Memory Elements and Clocking

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  1. Lecture 8Memory Elements and Clocking Hai Zhou ECE 303 Advanced Digital Design Spring 2002 ECE C03 Lecture 8

  2. Outline • Sequential logic networks • Latches (RS Latch) • Flip-flops (D and JK) • Timing issues (setup and hold times) • READING: Katz 6.1, 6.2, 6.3, Dewey 8.1, 8.2 ECE C03 Lecture 8

  3. Sequential Switching Networks Circuits with Feedback: Some outputs are also inputs Traffic Light Controller is a complex sequential logic network Sequential logic forms basis for building "memory" into circuits These memory elements are primitive sequential circuits ECE C03 Lecture 8

  4. Simple Circuits with Feedback Primitive memory elements created from cascaded gates Simplest gate component: inverter Basis for commercial static RAM designs Cross-coupled NOR gates and NAND gates also possible "1" Cascaded Inverters: Static Memory Cell "0" LD Selectively break feedback path to load new value into cell \LD \LD A Z LD ECE C03 Lecture 8

  5. RS Latch R S Q \ Q Just like cascaded inverters, with capability to force output to 0 (reset) or 1 (set) R S R Q S \Q Timing Waveform 100 Reset Hold Reset Set Race Set Forbidden State Forbidden State ECE C03 Lecture 8

  6. State Behavior of RS Latch Q Q Q Q Q Q Q Q 1 0 0 1 0 0 Truth Table Summary of R-S Latch Behavior 1 1 ECE C03 Lecture 8

  7. Theoretical RS Latch State Diagram Q Q Q Q Q Q Q Q SR = 00, 10 SR = 00, 01 SR = 1 0 1 0 0 1 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 SR = 1 1 0 0 SR = 0 1 SR = 1 0 SR = 0 0 SR = 0 0, 11 1 1 ECE C03 Lecture 8

  8. Observed RS Latch Behavior Q Q Q Q Q Q SR = 00, 10 SR = 00, 01 SR = 1 0 1 0 0 1 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 SR = 1 1 0 0 SR = 0 0 SR = 0 0 Very difficult to observe R-S Latch in the 1-1 state Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" ECE C03 Lecture 8

  9. Definition of Terms in Clocking T T su h Clock: Periodic Event, causes state of memory element to change rising edge, falling edge, high level, low level Input Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable Clock There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized Hold Time (Th) Minimum time after the clocking event during which the input must remain stable ECE C03 Lecture 8

  10. Level Sensitive RS Latch \ S \ Q \ R Level-Sensitive Latch aka Gated R-S Latch Schematic: Q \enb Timing Diagram: \S \R \enb Q \Q ECE C03 Lecture 8

  11. Latches vs Flip-flops Input/Output Behavior of Latches and Flipflops Type When Inputs are SampledWhen Outputs are Valid unclocked always propagation delay from latch input change level clock high propagation delay from sensitive (Tsu, Th around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) ECE C03 Lecture 8

  12. Latches vs Flipflops Positive edge-triggered flip-flop Level-sensitive latch 7474 D Q Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted Clk Timing Diagram: 7476 D Q D C Clk Clk Q 7474 Bubble here for negative edge triggered device Q 7476 Behavior the same unless input changes while the clock is high ECE C03 Lecture 8

  13. Timing Specifications of FFs T T T T su h su h 20 5 20 5 ns ns ns ns T w 25 ns T T plh phl 25 ns 40 ns 13 ns 25 ns 74LS74 Positive Edge Triggered D Flipflop D • Setup time • Hold time • Minimum clock width • Propagation delays (low to high, high to low, max and typical) Clk Q All measurements are made from the clocking event that is, the rising edge of the clock ECE C03 Lecture 8

  14. Timing Specifications of Latches T T T T su h su h 20 5 20 5 ns ns ns ns T w 20 ns T T plh phl C » Q C » Q 27 ns 25 ns 15 ns 14 ns T T plh phl D » Q D » Q 27 ns 16 ns 15 ns 7 ns 74LS76 Transparent Latch D • Setup time • Hold time • Minimum Clock Width • Propagation Delays: high to low, low to high, maximum, typical data to output clock to output Clk Q Measurements from falling clock edge or rising or falling data edge ECE C03 Lecture 8

  15. RS Latch Revisited Q ( t ) Truth Table: Next State = F(S, R, Current State) Derived K-Map: S SR S(t) R(t) Q(t) Q(t+d) 0 0 0 0 HOLD 0 0 1 1 ------------------------- 0 1 0 0 RESET 0 1 1 0 ------------------------- 1 0 0 1 SET 1 0 1 1 ------------------------- 1 1 0 X NOT ALLOWED 1 1 1 X 00 01 11 10 0 0 0 X 1 1 1 0 X 1 R Characteristic Equation: Q+ = S + R Q t S R-S Latch Q+ R Q ECE C03 Lecture 8

  16. JK Latch Design \ Q \ Q R-S latch How to eliminate the forbidden state? K R J(t) K(t) Q(t) Q(t+d) 0 0 0 0 HOLD 0 0 1 1 ------------------------- 0 1 0 0 RESET 0 1 1 0 ------------------------- 1 0 0 1 SET 1 0 1 1 ------------------------- 1 1 0 1 TOGGLE 1 1 1 0 J S Q Q Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle Characteristic Equation: Q+ = Q K + Q J ECE C03 Lecture 8

  17. JK Latch Race Condition J K Q \ Q Reset Set Toggle 100 Race Condition Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop ECE C03 Lecture 8

  18. Solution: Master Slave JK Flip Flop R-S R-S Latch Latch 1's Catch T oggle J K Clk P Master outputs \ P Q Slave \ Q outputs Master Stage Slave Stage \Q K \P \Q R R \Q S Q S Q P J Q Clk Sample inputs while clock low Sample inputs while clock high Uses time to break feedback path from outputs to inputs! Set Reset 100 Correct Toggle Operation ECE C03 Lecture 8

  19. Positive vs Negative Edge Triggered Devices D Clk Q pos Positive edge- t riggered FF \ Q pos Q neg Negative edge- t riggered FF \ Q neg 100 Positive Edge Triggered Inputs sampled on rising edge Outputs change after rising edge Negative Edge Triggered Inputs sampled on falling edge Outputs change after falling edge Toggle Flipflop Formed from J-K with both inputs wired together ECE C03 Lecture 8

  20. Realizing Circuits with Different Kinds of FFs R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(In,Q,Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!! ECE C03 Lecture 8

  21. Timing Methodology • Set of rules for interconnecting components and clocks • When followed, guarantee proper operation of system • Approach depends on building blocks used for memory elements For systems with latches: Narrow Width Clocking Multiphase Clocking (e.g., Two Phase Non-Overlapping) For systems with edge-triggered flipflops: Single Phase Clocking • Correct Timing: (1) correct inputs, with respect to time, are provided to the FFs (2) no FF changes more than once per clocking event ECE C03 Lecture 8

  22. Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register S,R are preset, preclear New value to first stage while second stage obtains current value of first stage IN Q0 Q1 D Q D Q C Q C Q CLK Correct Operation, assuming positive edge triggered FF ECE C03 Lecture 8

  23. Why Cascaded Flip-Flops Work T T su su 20 ns 20 ns Q 0 T T plh plh 13 ns 13 ns Q 1 T T h h 5 ns 5 ns • Propagation delays far exceed hold times; Clock width constraint exceeds setup time • This guarantees following stage will latch current value before it is replaced by new value • Assumes infinitely fast distribution of the clock In Timing constraints guarantee proper operation of cascaded components Clk ECE C03 Lecture 8

  24. Timing Methodologies Design Strategies for Minimizing Clock Skew Typical propagation delays for LS FFs: 13 ns Need substantial clock delay (on the order of 13 ns) for skew to be a problem in this relatively slow technology Nevertheless, the following are good design practices: • distribute clock signals in general direction of data flows • wire carrying the clock between two communicating components should be as short as possible • for multiphase clocked systems, distribute all clocks in similar wire paths; this minimizes the possibility of overlap • for the non-overlap clock generate, use the phase feedback signals from the furthest point in the circuit to which the clock is distributed; this guarantees that the phase is seen as low everywhere before it allows the next phase to go high ECE C03 Lecture 8

  25. Summary • Sequential logic networks • Latches (RS Latch) • Flip-flops (D and JK) • Timing issues (setup and hold times) • NEXT LECTURE: Registers and Counters • READING: Katz 7.1, 7.2, 7.4, 7.5, Dewey 10.2, 10.3, 10.4 ECE C03 Lecture 8

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