I/O PADS In, Out , InOut , Gnd , Vdd, Source follower
Bidirectional Pad -Digital Component. • Operates as Pad_in or Pad_out: • EO high => pad out. • EO low => pad in.
Pad Layout DataIn OE DataOut DataInBuf DataInUnBuf
Pad In DC Analysis DataInB, after one inverter, has less gain than dataIn
Max frequency 100Mhz • VinBar • Vin • Vpad • Dx = 4.11nsec (>80%*5=4nsec) • Cursers mark position where output exceed 80% of max input value
Pad out Dc Analysis • Response similar to dataIn. • Explanation: It has two levels of amplifying, as the dataIn node.
Max frequency 30Mhz with 10pF capacitor as load • Vpad • DataOut Dx = 14.06nsec (> 80%*17=13.6nsec) Cursors mark position where output exceed 80% of max input value
Sfwith no ideal current source • Function: Pad follows Signal, with DC offset.
SFLayout Vss Vdd Signal
SF behavior (with the pmos as current source) • Current source values -190 to -150 uA • 0<Vin<4 volt, the SF follow the input with 0.85 Voffset. 3.5V 4 V
Let’s have a closer look Vpad – Vsignal = 0.85 constant when 0 < Vsignal <= 4
Slew Rate of the SF • Vsignal • Vpad • Vpad-Vsignal Vsignal = ramp from 0 to 5v in 1usec The SF still follow the step in the range of 0<VSignal<4volt
Pad I/O With ESD D2 D1 • Two diodes are placed to protect the chip, and are normally at reverse charge. • When signal exceeds 5+Vb volts, then D2 is forward biased and discharges the excess voltage. • When signal is below –Vb, then a similar discharging process occurs through D1.
PadIOEsd Layout Diode 2 D2 in scehematic Diode 1 D1 in schematic signal
Modeling the Pad • The modeling was done by attaching a capacitor, and a resistor, to the pad. They reperesent the capacitance and resistance of three main models: Human, machine, and package. To run simulation, an initial voltage was initialized on the model.
Human model. R=1.5kΩ, C=100pF, Initial Voltage = 2kV
Machine Model. R=25Ω, C=200pF, Initial Voltage = 200V
Package Model R=1Ω, C=1.5pF, Initial Voltage = 2kV