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Shifter

Shifter. Lecture L7.4 Group HW #4 Section 10.3. MODULE shift TITLE 'shifter' DECLARATIONS " INPUT PINS " D3..D0 PIN 11,7,6,5; D = [D3..D0]; s2..s0 PIN 3,2,1; S = [s2..s0]; " OUTPUT PINS " Y3..Y0 PIN 40,41,43,44 ISTYPE 'com'; Y = [Y3..Y0]; noshift = [D3,D2,D1,D0];

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Shifter

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  1. Shifter Lecture L7.4 Group HW #4 Section 10.3

  2. MODULE shift TITLE 'shifter' DECLARATIONS " INPUT PINS " D3..D0 PIN 11,7,6,5; D = [D3..D0]; s2..s0 PIN 3,2,1; S = [s2..s0]; " OUTPUT PINS " Y3..Y0 PIN 40,41,43,44 ISTYPE 'com'; Y = [Y3..Y0]; noshift = [D3,D2,D1,D0]; shr = [0 ,D3,D2,D1]; shl = [D2,D1,D0,0 ]; ror = [D0,D3,D2,D1]; rol = [D2,D1,D0,D3]; asr = [D3,D3,D2,D1]; ror2 = [D1,D0,D3,D2]; EQUATIONS " Add when…else equations here "

  3. Mux Using Behavioral ABEL Z = !s2 & !s1 & !s0 & C0 # !s2 & !s1 & s0 & C1 # !s2 & s1 & !s0 & C2 # !s2 & s1 & s0 & C3 # s2 & !s1 & !s0 & C4 # s2 & !s1 & s0 & C5 # s2 & s1 & !s0 & C6 # s2 & s1 & s0 & C7

  4. MODULE mux81 TITLE '8 to 1 Multiplexer' DECLARATIONS " INPUT PINS " C7..C0 PIN 11,7,6,5,4,3,2,1; C = [C7..C0]; s2..s0 PIN 70,71,72; S = [s2..s0]; " OUTPUT PINS " Z PIN 35 ISTYPE 'com'; EQUATIONS when (S == 0) then Z = C0; when (S == 1) then Z = C1; when (S == 2) then Z = C2; when (S == 3) then Z = C3; when (S == 4) then Z = C4; when (S == 5) then Z = C5; when (S == 6) then Z = C6; when (S == 7) then Z = C7; @radix 16; test_vectors ([C,S] -> Z) [6,0] -> 0; [7,1] -> 1; [9,2] -> 0; [15,3] -> 0; [36,4] -> 1; [47,5] -> 0; [29,6] -> 0; [0A5,7] -> 1; END mux81.abl

  5. MODULE mux81 TITLE '8 to 1 Multiplexer' DECLARATIONS " INPUT PINS " C7..C0 PIN 11,7,6,5,4,3,2,1; C = [C7..C0]; s2..s0 PIN 70,71,72; S = [s2..s0]; " OUTPUT PINS " Z PIN 35 ISTYPE 'com';

  6. EQUATIONS when (S == 0) then Z = C0; when (S == 1) then Z = C1; when (S == 2) then Z = C2; when (S == 3) then Z = C3; when (S == 4) then Z = C4; when (S == 5) then Z = C5; when (S == 6) then Z = C6; when (S == 7) then Z = C7;

  7. D = [D3..D0]; S = [s2..s0]; Y = [Y3..Y0]; @radix 16; test_vectors ([D,S] -> Y) [0B,0] -> ___; [0B,1] -> ___; [0B,2] -> ___; [0B,3] -> ___; [0B,4] -> ___; [0B,5] -> ___; [0B,6] -> ___; [0B,7] -> ___; END

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