Placement: Hot or Not

1. Placement: Hot or Not Chuck Alpert Design Productivity Group Austin Research Laboratory

2. The State of Placement • Placement is an old problem • Rajeev: Today, the EDA academic community is not producing a lot of new ideas. Yes, at one time they did, but not today. • “Lou Scheffer” : place-and-route is in reasonable shape

3. Placement Trends (my guess, not scientific) 2010 2012 Chip gate count: 21 M Largest Block: 1.5 M Chip gate count: 76 M Largest Block: 3.7 M

4. Placement is Hot • Design sizes are exploding • Designers are embracing automation like never before • Secondary factors (power, area) become differentiating • Wirelength is no longer primary • Congestion • Timing • Power • Clock-friendly

5. Generic Design Flow From Cadence

6. Vt Optimization? Swap to lower vt

7. a e c d d f b Gate Sizing or Repowering c a e b f

8. Buffering and Layer Assignment

9. a e c d f b g Inverter Absorption / Decomposition a e f b

10. Composition / Decomposition w Out x w AOI nd2 B x Out nd2 A y nd2 C y nd2 C z z D D Courtesy: Louise Trevillian, founder of Logic Synthesis

11. Example Timing Closure “Optimization” Critical Path Optimization While 500 most critical nets still optimizable Gate sizing and vt Optimization Buffering on sub-tree Buffering on entire tree Congestion-aware layer assignment Suite of logic transforms Compression Optimization For remaining critical nets Gate sizing and vt Optimization Buffering, layer assignment on sub-tree

12. What Timing-Driven Placement Means Weight all nets? If not, what percent? What weight range? What netlist state for timing-driven placement?

13. Over Weight Can Destroy Congestion Initial After Timing-driven Placement Optimization Placement

14. Don’t Put Timing into Placement! Timing-driven Placement Flow Placement Timing Easy Constraints Placement Incremental Placement Constraint Generation Timing

15. Example Incremental Timing-Driven Placement Initial Final

16. Techniques Required for Timing-Driven Placement • Identification of “easy” constraints • Incremental Placement • Shorten critical paths without hurting other paths • Fast, incremental wirelength recovery • Congestion-preserving detailed placement (don’t pack!) • Getting pipeline latches right • Meaningful timing model • Interleave optimization (e.g., layer assignment)

17. Pipeline Latch Placement

18. Pipeline Latch Placement

19. Logic Logic Interference From Other Logic

20. Power-Aware Placement #nets Switching Factor

21. Congestion Still Huge Problem • Contests focus on congestion-driven placement • Also need for incremental congestion repair • Fast, accurate congestion modeling is key Placement A Placement B Placement A Placement B Router 1 Router 2

22. Placement Density Reasonable First Order

23. Local Congestion Effects (Pin Density) After Spreading Before Spreading

24. Handling Movebounds

26. Move Bound Challenges • Don’t increase runtime • High density / low density • Inclusive or exclusive • OverlappingSoft or absolute • Different shapes • Support high quantity

27. ( net1 Fixed pins Base Run Soft Alignment Forced Alignment net1 net1 Datapath Placement LEGAL HPWL = 2513500 LEGAL HPWL = 2461745 LEGAL HPWL = 2385800 Courtesy: Sam Ward

28. Latch Huddling: Good For Clock Skew and Power

29. Why Huddling is Good for Clocks Less Clock Wire More Clock Wire

30. All Object Movement (Before and After Huddling) movement (in tracks) 1-5050-100 100-200 200-500 500+ Incremental Huddling Placement Global Huddling Placement

31. Global Clock Trees Challenge, can we separate three trees to prevent routing overlap?

32. Proposed Placement Framework • Keep placement as a stand alone optimization • Enrich it to handle constraints • Add constraint generation step to guide placement • Move bounds • Power Switching factors • Tightness of latch huddles • Clock domain separation • Use of hierarchical name space • Alignment of datapath

33. Proposed Placement Flow Pre-Placement Constraints Placement (Global or Incremental) Clock Analysis Congestion Analysis Power Analysis Timing Analysis Constraint Generation

34. Do We Need to Write a Placer from Scratch? Clustering Clustered Global Flat Global Pin-Density Spreading Density Spreading Fast Congestion Analysis Congestion Mitigation Congestion-aware Detailed Placement Power Reduction

35. Chasing the Hot Topics Instead of trying to predict the next important problem Just ask (a designer)