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Chapter 3

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Chapter 3. Logic Gates By Taweesak Reungpeerakul. Contents. Inverter AND Gate OR Gate NAND Gate NOR Gate XOR and XNOR Gates Integrated Circuit Logic Gates. Symbols Truth Table In Out 0 1 1 0. Timing Diagram Logic Expression: Out = In. 3.1 Inverter (INV). 0. 1. 1.

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Chapter 3

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  1. Chapter 3 Logic Gates By Taweesak Reungpeerakul 241-208 CH3

  2. Contents • Inverter • AND Gate • OR Gate • NAND Gate • NOR Gate • XOR and XNOR Gates • Integrated Circuit Logic Gates 241-208 CH3

  3. Symbols Truth Table In Out 0 1 1 0 Timing Diagram Logic Expression: Out = In 3.1 Inverter (INV) 0 1 1 0 241-208 CH3

  4. Symbols Truth Table A B Out 0 0 0 0 1 0 1 0 0 1 1 1 Timing Diagram Logic Expression: Out = AB 3.2 AND Gate 241-208 CH3

  5. Symbols Truth Table A B Out 0 0 0 0 1 1 1 0 1 1 1 1 Timing Diagram Logic Expression: Out = A+B 3.3 OR Gate 241-208 CH3

  6. Symbols Truth Table A B Out 0 0 1 0 1 1 1 0 1 1 1 0 Timing Diagram Logic Expression: Out = AB 3.4 NAND Gate 241-208 CH3

  7. Symbols Truth Table A B Out 0 0 1 0 1 0 1 0 0 1 1 0 Timing Diagram Logic Expression: Out = A+B 3.5 NOR Gate 241-208 CH3

  8. Symbols Truth Table A B Out 0 0 0 0 1 1 1 0 1 1 1 0 Timing Diagram Logic Expression: Out = AB+AB; AB 3.6 XOR Gate 241-208 CH3

  9. Symbols Truth Table A B Out 0 0 1 0 1 0 1 0 0 1 1 1 Timing Diagram Logic Expression: Out = AB+AB; AB XNOR Gate 241-208 CH3

  10. CMOS: Complementary Metal-Oxide Semiconductor Low Power Dissipation DC Power Supply: 5 V & 3.3 V CMOS Series: 74(or 54) + letter(s) + numbers Letters: HC, HCT = High-speed CMOS LV, LVC = Low-voltage CMOS BCT = BiCMOS (combine CMOS&TTL) Numbers: 00= Quad 2-input NAND 02= Quad 2-input NOR 04= Hex inverter TTL: Transistor-Transistor Logic Not Sensitive to Electrostatic Discharge Switching Speed DC Power Supply: 5 V TTL Series: 74 (or 54) + letter(s) + numbers Letters: S = Schottky TTL LS = Low-power Schottky TTL F = Fast TTL Numbers: 08= Quad 2-input AND 10= Triple 3-input NAND 32= Quad 2-input OR 3.7 Integrated Circuit Logic Gates 241-208 CH3

  11. Packages DIP, SMD IC Gate Config. 3.7 IC Logic Gate (cont.) PBGA DIP TSSOP LQFP TQFP 241-208 CH3

  12. Propagation Delay Time: tP , tPHL , tPLH Performance Characteristics & Parameters 241-208 CH3

  13. DC Power Supply: 3.3 (CMOS), 5V (CMOS or TTL) Performance Characteristics & Parameters (cont.) Retrieved from Motorola SN74LS00 241-208 CH3

  14. Fan-out and Loading indicates the number of loads that can be connected if a logic IC drives several loads with the same characteristics. Performance Characteristics & Parameters (cont.) For TTL device:- Unit loads (HIGH Logic) = IOH/IIH Unit loads (LOW logic) = IOL/IIL 241-208 CH3

  15. Power Dissipation (PD) PD = VCC (ICCH+ICCL)/2 Performance Characteristics & Parameters (cont.) 241-208 CH3

  16. I/O Logic Levels TTL: VIL =0.8 V, VIH =2 V VOL =0.4 V, VOH =2.4V Performance Characteristics & Parameters (cont.) 241-208 CH3

  17. Performance Characteristics & Parameters (cont.) • Speed-power Product (SPP) SPP = tP*PD (Joul unit) Homework Lists (pp.153-158) 1,3,5,9,11,13,15,20,25,27,28,39,40,43 Assignments:- 241-208 CH3

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