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CPU08 INTRODUCTION

CPU08 INTRODUCTION. CPU08. IRQ. LVI. Direct Memory Access Module (DMA). System Integration Module (SIM). Clock Generation Module (CGM). Timer Interface Module (TIM). 68HC08 CPU. RESET. COP. BREAK. Internal Bus (IBUS). Random Access Memory (RAM). Serial Peripheral

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CPU08 INTRODUCTION

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  1. CPU08INTRODUCTION

  2. CPU08 IRQ LVI Direct Memory Access Module (DMA) System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) 68HC08 CPU RESET COP BREAK Internal Bus (IBUS) Random Access Memory (RAM) Serial Peripheral Interface (SPI) Electronically Programmable Memory (EPROM) Monitor ROM Serial Communications Interface (SCI)

  3. Module Exercise Objectives • At end of sections coming up, will write • Subroutine that clears all RAM locations • Code sequence that executes at Power-on or RESET and calls the RAM clearing subroutine

  4. CPU08EXECUTIONARCHITECTURE

  5. CPU08 Execution Architecture • CPU08 is divided into two blocks • Control unit • Contains a finite state machine, control and timing units that drive the execution unit • Execution unit • Contains the ALU, registers, and bus interface

  6. T1 T2 T3 T4 CYCLE 1 CYCLE 2 T1 T2 T3 T4 T1 T2 T3 T4 CPU Clock Internal Addr. Cycle N Address Bus Internal Data Cycle Data Bus Execute Cycle N Iternal Timing CPU08 derives its timing from a four phase clock CPU bus cycle consists of one clock pulse from each phase • Cycle 1 T1,T2 - new address is calculatedCycle 2 T2 - Data is read for this address • Addresses lead the data by one-half bus cycle

  7. CPU08 Prefetch • HC05 has many cycles where the address and data bus are idle • CPU08 contains an opcode "look ahead" prefetch mechanism • Performance increases were achieved by removing as many dead bus cycles as possible. • CPU08 instruction flow was developed to be as efficient as possible in a pipelined architecture

  8. Instruction Execution • All instructions: • Execute in a finite number of bus cycles • See individual instructions for number of bus cycles • Load next opcode into Opcode Lookahead register • Increment the Program Counter to next location • Happens after prefetch • Program Counter will be pointing to byte following prefetched opcode

  9. Control Signals • Two Control Unit signals control prefetch and instruction loading • Opcode Lookahead • Signals prefetch operation • Lastbox • Signals last cycle of current instruction

  10. Instruction Execution TimingExample ORG $50 FCB $12, $34, $56 ORG $100 0100 A6 50 LDA #$50 ;A=$50 PC=$0103 0102 97 TAX ;A --> X PC=$0104 0103 E6 02 LDA 2,X ;[X+2] --> A PC=$0106 0105 5C INCX ;X=X+1 PC=$0107 0106 C7 80 00 STA $8000 ;A --> $8000 PC=$010A

  11. T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 CPU Clock Opcode TAX Lookahead LDA Opcode INCX Opcode Opcode Register Lastbox Opcode Lookahead IR/Control Unit TAX LDA State 1 LDA State 2 LDA State 3 INCX State 1 State Input State 1 Control Unit LDA Cycle LDA Cycle LDA Cycle 1 Strobe 2 Strobe 3 Strobe Strobe Control Unit LDA Cycle 1 LDA Cycle 2 LDA Cycle 3 Output to TAX EU Control EU Control EU Control EU Control Execution Unit LDA Opcode LDA Offset INCX Opcode LDA Operand STA Opcode Prefetch Fetch Prefetch Read Prefetch Internal $0103 $0104 $0105 $0052 $0106 Address Bus LDA Opcode INCX Opcode Internal $E6 $02 $5C $56 Data Bus Instruction Execution TAX LDA Boundaries Instruction Execution Timing Example

  12. Programming Model Accumulator (A) Index Register (H:X) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR)

  13. Condition Code Registers Bits • V - Two’s complement overflow flag • Set if a signed arithmetic operation has overflowed • Utilized in checking signed arithmetic operations • H - Half Carry flag • Set if a carry occurred from bit 3 to bit 4 • Utilized in Binary Code Decimal (BCD) operations • I - Global Interrupt Mask • When set, disables CPU interrupts • N - Negative • Set if bit 7 is set in the Accumulator • Z - Zero flag • Set if all bits in the Accumulator are clear • C - Carry or Borrow flag • Set if a carry or borrow occurred during an operation

  14. C 255 80 81 HC08-PrgMdlSol H N Z C H N Z C - FF 7F +127 unsigned 00 + $01 00 $FF - $80 $70 01 01 4. 3. CCR STATUS FLAGS 01 +1 7F +1 +127 00 7E 0 signed 0 0 modulo 7F number line C -1 H N Z C H N Z C FF -1 C -128 80 -2 FE + $FF + $01 $80 $7F Number lines: 2. 1. and signed Exercises: unsigned FE -128 FF

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