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Towards Large On-Chip Caches: Optimizing Lookups with Cache RegionTracker

Explore how Cache RegionTracker optimizes cache lookups, improves cache latency, reduces power usage, and enhances memory access efficiency. Learn about the design, benefits, and impact of implementing cache region tracking in on-chip caches.

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Towards Large On-Chip Caches: Optimizing Lookups with Cache RegionTracker

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  1. RegionTracker:Optimizing On-Chip Cache Lookups

  2. What is a Cache? Memory Either Big & Slow or Small & Fast CPU Fast Big & Slow Memory Small & Fast CPU Cache

  3. How Does a Cache Work? Address: Tag Array Data Array = = = = Select

  4. Towards Large On-Chip Caches Memory: CPU: CPU Cache CPU 1989 1971

  5. Towards Large On-Chip Caches CPU CPU CPU CPU CPU Cache Cache 1995 2006 CPU CPU CPU CPU • Larger, Slower caches • How can we make caches Fast again?

  6. Tag Lookup Plays Critical Role • Larger Caches are Slower, and use More Power • Serial Tag-Data lookup to reduce power CPU • Search for Tag in Tag Array • Then read desired block from data array Tag Array Data Array • Lots of fine-grain information • Can We Improve This?

  7. Key Insight Memory • Only a fewregions in cache at a time. • Can we use something small and fast to track these regions? Cache

  8. RegionTracker Design 4 • Cached Block Vector (CBV) • Cached Region Hash (CRH) (not shown) • Track which Regions are currently Cached • Allocated new CBV entry on access to new region • Combine Coarse-Grain and Fine-Grain Information 28

  9. Results and Insights • Takes advantage of common program behavior • Access a few large, continuous areas of memory at a time • Simple, Small Structures • Compact Information Encoding & Fast Access • Still use tag array when RegionTracker misses • Reduces Cache Latency • Can Reduce Cache Lookup Power • Software does NOT change

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