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期中考範圍

期中考範圍. 賴秉樑. PING-LIANG LAI . 共考 4 題，每題 25 分. 第一題. 給定一組合電路，求出 Fault Collapsing 後的 Fault list 。. Fault Equivalence Rule. AND gate: all s-a-0 faults are equivalent OR gate: all s-a-1 faults are equivalent NAND gate: all the input s-a-0 faults and the output s-a-1 faults are equivalent

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期中考範圍

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  1. 期中考範圍 賴秉樑 PING-LIANG LAI 

  2. 共考4題，每題25分

  3. 第一題 • 給定一組合電路，求出Fault Collapsing後的Fault list。

  4. Fault Equivalence Rule • AND gate: all s-a-0 faults are equivalent • OR gate: all s-a-1 faults are equivalent • NAND gate: all the input s-a-0 faults and the output s-a-1 faults are equivalent • NOR gate: all input s-a-1 faults and the output s-a-0 faults are equivalent • Inverter: input s-a-1and output s-a-0 are equivalent input s-a-0 and output s-a-1 are equivalent SA1 SA0 SA1 SA0 SA0 SA1 SA0 SA1 SA0 SA1 SA1 SA0 SA1 SA0 SA0 SA1 SA0 SA1 SA1 SA0 SA0 SA1 SA1 SA0 SA1 SA0 n+2 instead of 2n+2 faults need to be considered for an n-input gate. SA0 SA1

  5. Fault Collapsing Summary • Given F1 and F2 with T1 and T2 • Equivalence • F1 is equivalent to F2 if T1 = T2 • Any test detecting F1, detects F2 and vice versa • Dominance • F1 dominates F2 if T2 Í T1 • A test detecting F2 detects also F1 • The relation is not symmetric Example: NAND2 A C B Fault equivalence: {A/0, B/0, C/1} Fault dominance: A/1 → C/0, B/1 → C/0 Fault collapsing: {A/0, A/1, B/1}

  6. An Example of Fault Collapsing A • A step of collapsing • {A/0, B/0, H/0} • {C/1, D/1, F/1} • {G/0, E/0, V/0} • {H/1, V/1, Z/1} • {F/0, G/1} • {F/1, G/0} • A/1 → H/1, thus A/1 can represent H/1 and all its equivalent faults in class 4 • C/0 → F/0, thus C/0 can represent F/0 and all its equivalent faults in class 5 • G/1 → V/1, thus G/1 can represent V/1 and all its equivalent faults in class 4 • H/0 → Z/0, thus H/0 belongs to equivalence class 1 • B/1 → H/1 • D/0 → F/0 • E/1 → V/1 • V/0 → Z/0 • {A/0, C/1, G/0, A/1, C/0, G/1, B/1, D/0, E/1} → Final set of fault under test H B Z G F C V D E

  7. 第二題 • 找出TransistorStuck-open或Stuck-short的測試向量。

  8. Transistor Faults (1/4) • MOS transistor is considered as an ideal switch and two types of faults are modeled: • Stuck-open: a single transistor is permanently stuck in the open state • Stuck-short: a single transistor is permanently shorted irrespective of it's gate voltage • Detection of a stuck-open fault requires a two vector sequence Vector 2: test for A SA1 A 0 1 PMOS stuck-open fault Faulty circuit states B 0 0 1 (Z) C 0 Vector 1: test for A SA0 (initialization vector) Good circuit states Transistor stuck-open fault

  9. Transistor Faults (2/4) • Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ) Vector 2: test for A SA0 A 1 PMOS stuck-short fault Faulty circuit output B 0 1 (X) C Good circuit output IDDQ path in faulty circuit Transistor stuck-short fault

  10. 第三題 • 給定一組合電路，TM。

  11. An Example of Combinational Circuit (1/3)

  12. An Example of Combinational Circuit (2/3) First, calculate the TM for the nodes on the second level, F, H, and G • CC1(F)=CC1(A)+CC1(B)+CC1(C)+1=4 • CC0(F)=min{CC0(A), CC0(B), CC0(C)}+1=2 • CC1(H)=min{CC0(A), CC0(B)}+1=2 • CC0(H)=CC1(A)+CC1(B)+1=3 • CC1(G)=CC0(C)+1=2 • CC0(G)=CC1(C)+1=2 These TM values are then used in calculating the primary output controllability • CC1(Y)=min{CC1(F), CC1(H)}+1=3 • CC0(Y)=CC0(F)+CC0(H)+1=6 • CC1(Z)=min{CC0(H), CC0(G)}+1=3 • CC0(Z)=CC1(H)+CC1(G)+1=5

  13. An Example of Combinational Circuit (3/3) The observability of a node indicates the effort needed to observe the logic value on the node at a primary output For second level, • COY(F)=CO(Y)+CCO(H)+1=5 • COZ(G)=CO(Z)+CC1(H)+1=4 • COY(H)=CO(Y)+CC0(F)+1=4 • COZ(H)=CO(Z)+CC1(G)+1=5 For primary inputs, • COZ(C)=COZ(G)+1=[CO(Z)+CC1(H)+1]+1 =5 (line C) • COY(C)=COY(F)+CC1(A)+CC1(B)+1 =[CO(Y)+CC0(H)+1]+CC1(A)+CC1(B)+1=8 (line C) • COYH(A)=COY(H)+CC1(B)+1=6 • COZ(A)=COZ(H)+CC1(G)+1=8 CC1(F)=4 CC0(F)=2 CC1(H)=2 CC0(H)=3 CC1(G)=2 CC0(G)=2 CC1(Y)=3 CC0(Y)=6 CC1(Z)=3 CC0(Z)=5

  14. 第四題 • 給定一循序電路，劃出Scan DFT的設計電路。

  15. Example: Scan for Binary Counters • 3-bits Counter using DFF - State table As function of F(A,B,C) DA=A⊕BC DB=B⊕C DC=C’

  16. Scan DFT for Binary Counters (1/2) • 3-bits Binary Counters Next State and Output Combinational Logic CUT DA=A⊕BC DB=B⊕C DC=C’ C B 1 A DC DB DA CLK

  17. Scan DFT for Binary Counters (2/2) C B IN/SI 0 0 0 0 1 1 1 1 A/SO CLK SE

  18. S: Shift operation C: Capture operation H: Hold cycle V1:PI V2:PI SE S H C H S H C CLK V1:SI (PPI) V2:SI (PPI) SO (PPO) observation C (PO) observation

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