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Performance Challenges of Future DRAM´s

Performance Challenges of Future DRAM´s. SINANO WS, Munich, Sept. 14th, 2007. M. Goldbach / J. Faul. Content. Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion. Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion.

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Performance Challenges of Future DRAM´s

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  1. Performance Challenges of Future DRAM´s SINANO WS, Munich, Sept. 14th, 2007 M. Goldbach / J. Faul

  2. Content • Introduction • DRAM Challenges • Array Device Scaling • Support Device Scaling • Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 2

  3. Introduction • DRAM Challenges • Array Device Scaling • Support Device Scaling • Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 3

  4. 0.7x 250  180  130  90  65  45  32  22 HP logic 0.5x Introduction I MOS Transistor Scaling (1974 to present): Half Pitch Pitch HP logic: Speed & area driven DRAM: Area & speed driven  more nodes, however smaller steps Note: Scaling refers to gate half Pitch in nm Qimonda · M. Goldbach · Month Date, Year · Page 4

  5. Introduction II ITRS Roadmap 2001: Scaling continues, however, logic scaling slowed down to 3 yrs cycle Qimonda · M. Goldbach · Month Date, Year · Page 5

  6. Introduction III Scaling history for - power-supply voltage Vdd - threshold voltage Vt - gate oxide thickness tox  Vdd, Vt and tox saturate! Key Question: Are we approaching the limit of silicon scaling!? Qimonda · M. Goldbach · Month Date, Year · Page 6

  7. Introduction IV Power Consumption: Both, passive and active power density increase 8” hot plate at 1500W Ref. 1 Reason: Demand for ever increasing performances Qimonda · M. Goldbach · Month Date, Year · Page 7

  8. Introduction • DRAM Challenges • Array Device Scaling • Support Device Scaling • Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 8

  9. DRAM Challenges I (Architectures) DRAM´s are offered in various densities & architectures: Synchronous DRAM: Data, commands, and addresses synchronized with clock Single data rate (SDR) Double data rate (DDR) Double data rate II (DDR II) Clock DRAM Adresses Data (DQ) Commands Clock Vdd Vss Vddq Vssq Simplified Block Diagram DRAM Data SDR Data DDR Data DDR II (double freq) Commands DDRII Qimonda · M. Goldbach · Month Date, Year · Page 9

  10. DRAM Challenges II (Speed Classes) Ref. 2 For DDR, data rate 2x clock frequency (both graphics and main memory) Qimonda · M. Goldbach · Month Date, Year · Page 10

  11. DRAM Challenges III (Array Access) • Array Access: • tAA ~ Tpd • Higher densities: More speed critical • speed depends on parasitics • tAA: Array Access Time • Tpd: Propagation delay Ref. 2 Qimonda · M. Goldbach · Month Date, Year · Page 11

  12. DRAM Challenges IV(General Remarks) • Strong Interaction Array / Support Device Design • - Defect Treatment • Required for long data retention, however, limited doping activation • - Structuring • Structure both, dense array and logic circuits in same steps • - Density / Aspect ratios • Driven by very dense cell areas • - Low leakage requirements • Junction leakage < 1fA per node in array • Array transistor: < 1fA to ensure data retention Support transistors: Ioff ~10pA/µm (high speed logic ~100nA/µm) • Low Complexity & overall costs Qimonda · M. Goldbach · Month Date, Year · Page 12

  13. Introduction • DRAM Challenges • Array Device Scaling • Support Device Scaling • Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 13

  14. Reverse Forward Array Device Scaling I (Asymmetric Device) • Asymmetric Device: Low Node leakage & low Ioff • by asymmetric well doping DRAM cell schematics Asymmetric cell device Reverse: Source @ Node Forward: Source @ Bit Line (BL) - contact Ref. 5 Qimonda · M. Goldbach · Month Date, Year · Page 14

  15. Array Device Scaling II (EUD Device) • All major DRAM companies convert from planar to 3D devices in the 60-90nm nodes • Example: Qimonda´s Extended U-shape device (EUD) X-section width device (parallel WL) X-section along device (perpendicular WL) Ref. 3 Qimonda · M. Goldbach · Month Date, Year · Page 15

  16. Array Device Scaling III (EUD Device) Transfer Characteristics Data retention Characteristics Target Vnwll Side gate device Impact • Introduction of EUD for node field reduction • (no current gain expected) • Current modification by side gate Ref. 3 Qimonda · M. Goldbach · Month Date, Year · Page 16

  17. Array Device Scaling IV (FinFet in Array) Potential Future: FinFet in array X-section along device (perpendicular WL) No body effect X-section width device (parallel WL) Fig.12: Measured FinFET Ids-Vgate characteristics of the 90nm demonstrator for different p-well voltage (Vpw). • Motivation for FinFet: • Slope of 80mV/dec @ 85°C achieved • Ids of ~ 30µA achieved • no Body effect Ref. 4 Qimonda · M. Goldbach · Month Date, Year · Page 17

  18. Array Device Scaling V (Array Path) Ref. 2 Qimonda · M. Goldbach · Month Date, Year · Page 18

  19. Introduction • DRAM Challenges • Array Device Scaling • Support Device Scaling • Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 19

  20. Support Device Scaling I (History) • DRAM Support Device Scaling: • Lpoly scales by ~0.5x every 3 years • DRAM support transistors longer than • high speed logic devices but comparable to low standby power • Since ~ 2006: Lpoly(pf) = Lpoly(nf) • (Dual gate work function processes) • Off current constraints: • Logic Lpoly scaling slows down • Lpoly scaling drives scaling of other properties as well DRAM Ref. 5 Qimonda · M. Goldbach · Month Date, Year · Page 20

  21. Scaling Topics Issues Support Device Scaling II (Topics & Issues) Ref. 2 Qimonda · M. Goldbach · Month Date, Year · Page 21

  22. Support Device Scaling III (Gox scaling) Gate Oxide Scaling: • Direct tunnelling thru dielectric • Ig(nf) ~ 1.5 dec higher than Ig(pf) • (Reason: Hole vs. electron tunneling) • Ig / tox ~ 1dec / 2 Angstrom • For tox  2.5nm Ig uncritical • (Ig < 10pA/µm²) • Between 2 < tox < 2.5nm • Ig needs to be considered • Below 2nm: High k gate dielectrics might be employed Ref. 6 (Eqivalent oxide thickness (EOT)) Gate Oxide Leakage: Ig(tox) = A0 exp(–B0tox) Qimonda · M. Goldbach · Month Date, Year · Page 22

  23. Support Device Scaling IV (Scaling Path) Ref. 2 Qimonda · M. Goldbach · Month Date, Year · Page 23

  24. Introduction • DRAM Challenges • Array Device Scaling • Support Device Scaling • Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 24

  25. Scaling of Si technology not yet reached  will continue down below 30nm ground rules Unlike logic, DRAM support device design obey array driven limitations (e.g. doping activation, structuring, low leakage requirements) Array device scaling path: conventional  asymmetric doping  3D structures Support device scaling path: conventional  adaptions (e.g. stress, high k)  3D structures Conclusion Qimonda · M. Goldbach · Month Date, Year · Page 25

  26. “Silicon CMOS devices beyond scaling”, W. Hänsch et al., IBM J. of Res. and Dev. 50, 2006. DRAM short course, VLSI 2007, by S. Hong. “A 58nm Trench DRAM Technology”, T. Tran et al., IEDM 2006. “DRAM Scaling Roadmap to 40nm”, W. Müller et al., IEDM 2005. “Transistor Challenges – A DRAM Perspective”, J. Faul et al., NIM in Phys. Res. B 237 (2005) 228-234. “Ultra Low Power SRAM technology”, R.W. Mann et al., IBM J. of Res. and Dev. 47, 2003. References Qimonda · M. Goldbach · Month Date, Year · Page 26

  27. Thank you The World’s LeadingCreative Memory Company

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