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FPLDS Introduction

FPLDS Introduction. What is Programmable Logic?. Circa 1970 -- TTL Design. Design a logic circuit that implements the function. 74HC04. 74HC32. 74HC08. Design is done “by hand” using TTL DataBook. Verification is performed using a “breadboard.”. TTL Design.

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FPLDS Introduction

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  1. FPLDS Introduction

  2. What is Programmable Logic? Circa 1970 -- TTL Design Design a logic circuit that implements the function 74HC04 74HC32 74HC08 Design is done “by hand” using TTL DataBook. Verification is performed using a “breadboard.”

  3. TTL Design We need three separate Dual Inline Package (DIP) TTL packages to implement this design in hardware. Note, because of the multiple components this design consumes power, board space is costly, hard to debug and manufacture.

  4. FPLD Design In field programmable logic device (FPLD) design (FPLD), we use a computer aided design (CAD) software tool (e.g. QUARTUS II) to perform “design entry.” We can also use the same package for “design verification” and also to “download” the “design program” into hardware (i.e. the PLD). Our design now becomes: This single chip design requires Less power, less board space, should cost less on a per gate basis, is easier to debug (in software), and be easier to manufacture. Also, Intellectual Property (IP) can be protected and exploited using a FPLD.

  5. Benefits of FPLD Design • Increased system performance (Speed) • This is due to the reduced interconnect distances between gates. In a • TTL design we have large RC delays as we propagate signals from one chip • to another. In FPLD designs, this distances are in the um range. Large Delay on this net FPLD Design The same net is now internal to the FPLD

  6. Benefits of FPLD Design • Increased Gate Density • More logic gates on each FPLD implies that you can have more functionality per unit area of board space. A single FPLDs/FPGAs can hold the equivalent of over 1 million TTL logic gates. • Reduced Development Time • CAD tools significantly reduce the development time for new designs. This not only cuts down the “time to market,” but also allows reduces the size of the team needed to complete a design.

  7. Benefits of FPLD Design • Rapid Hardware Prototyping • Hardware prototyping is greatly simplified using FPLDs because it is relatively easy to change the design. One major concern however is I/O pin assignments. • Reduced “Time to Market” • Since FPLDs are already “complete,” there is no need to wait for fabrication.

  8. Benefits of FPLD Design • Future Modifications • Since FPLDs can be “reconfigured” in the field. It is possible to have the end user perform system “upgrades.” • Reduced Inventory Risk • The same type of FPLD can be used in multiple • designs, so the inventory risk is significantly reduced.

  9. Benefits of FPLD Design • Reduced Development Costs • The development costs for FPLDs tend to be lower than Application Specific Integrated Circuits (ASICs); however, the per unit cost of a FPLD is higher than an ASIC for large volumes.

  10. Shorthand Notation Programmable Interconnect at each node. Blue dot means a connection has been made.

  11. Shorthand Notation (Cont)

  12. Programmable Logic Array (PAL) AND-OR Architecture Inputs Outputs

  13. PAL Example P R O D U C T AND Plane (Prog) T E R M S OR Plane (Fixed) SUM TERMS

  14. PAL Example We can use a PAL to implement Sum-of-Products (SOP) Logic Example: Use a PAL to design a logic circuit which implements Note: In our PAL, we have the “fixed” logic

  15. PAL Example Let’s “program” the AND Array (or AND plane), so that Since, We find,

  16. Programmable Interconnects PAL Example AND Plane (Prog) OR Plane (Fixed)

  17. PAL Example We can use the same type of device to “program” Let

  18. Programmable Interconnects PAL Example OR Plane (Fixed)

  19. What about term? PAL Example However, what if, I want Let I’ve run out of pterms!!! Need to pick a bigger PAL!!!

  20. Survey of FPLDs PALs Ex: 16V8 Circa: 1978 Inputs Outputs

  21. Survey of FPLDs Simple PLDs Add programmable I/O “macrocells” to PAL architecture. I/O Macrocells contain registers. Ex: 22V10 Circa: 1980

  22. Survey of FPLDs Complex PLDs “Mini” PALs, programmable with registers called Logic Array Blocks (LABS) are interconnected using a Programmable Interconnect Array (PIA). Altera’s Max-5032 Max-7032 Circa: 1985 LAB=Logic Array Block (prog) PIA = Prog. Interconnect Array

  23. Survey of FPLDs Field Programmable Gate Arrays (FPGAs) An array of “small” blocks of programmable logic within an Vendors Xilinx (Actel) Circa: 1990 Programmable Interconnects Connects LCs to routing channels Routing Channels I/O = Input/Output Cell LC=Logic Cell

  24. Survey of FPLDs System-on Programmable Chip (SOPC) Combines Programmable Logic with embedded Static Random Access Memory (SRAM) on the same Integrated Circuit (IC). Circa: 2000 to Now!! Altera and Xilinx

  25. Programming Elements - PE PEs are used to physically “program” the interconnects. FET acts like a “switch” If Vgate is ONE, switch is closed, connecting A and B otherwise A and B are isolated. Field Effect Transistor (FET)

  26. Programming Elements - PE Example Closed Open Vgate=One Switch Closed Vgate=Zero Switch Open

  27. Programming Elements - PE So, we’ll have one FET at every programmable Interconnect, but we need a method or technique to “program” VGATE to be ONE or ZERO. Before, we look at our options, some definitions

  28. Programming Elements - PE Two Types: 1. Volatile “Program” is lost when power is removed 2. Non-volatile “Program” is retained with power is removed. Two Classes: 1. Re-programmable PE can be “erased” and “re-programmed” 2. One-time-programmable (OTP) PE can only be programmed “one” time. (not really used anymore)

  29. Programming Technologies EPROM – Erasable Programmable Read Only Memory Reprogrammable and non-volatile It is possible to physically program an EPROM cell to always be ONE when power is applied. Also, we can use ultraviolet (UV) light to reset or “erase” the EPROM cell back to ZERO. Ex: Max-5000

  30. Programming TechnologiesEPROM UV To erase We can, therefore, erase all the cells of the EPROM and then program the PEs that we want to be ONEs.

  31. Programming Technologies EEPROM – (E2PROM) Electrically Erasable Programmable Read Only Memory Reprogrammable and non-volatile Similar to an EPROM except cell can be “erased” electrically. Ex: MAX-7000 family

  32. Programming Technologies • SRAM • Static Random Access Memory • Volatile and Reprogrammable (electrically) SRAM Cell To Vgate Store the value of VGATE within a SRAM cell. We lose the program whenever the power is removed. Therefore, we’ll need the ability to “reload” the design upon power-up.

  33. SRAM CELLWrite Write 0 Write 1 1 0 1 0 0 0 1 1 1 1 WL=1, turns “ON” FET, connecting BL to the cell

  34. SRAM CELLRead Read X data data data 0 WL=0, turns “OFF” FET, isolating data from the cell. However, Due to “positive” feedback, data is retained in the memory cell until power is removed

  35. Programming TechnologiesSRAM Use a SRAM cell to store VGATE. Lose “program” when power is removed.

  36. Programming Technologies Anti-Fuse Non-volatile and OTP Normally, anti-fuse behaves like an “open” circuit, however you can “destroy” the fuse electrically so that it behaves like a short circuit. Anti-fuse The antifuse is very small compared to the other PEs. .

  37. Summary FPLD Benefits • Increased Performance • Increased Gate Density • Reduced Development Time • Rapid Hardware Prototyping • Reduced “Time to Market” • Future Modifications • Reduced Inventory Risks • Reduced Development Costs

  38. Summary FPLD Types • PALS • Simple PLDs • Complex PLDs (FPLDs) • FPGAs • SOPC

  39. Summary Programming Elements Types: Classes: • Reprogrammable • OTP • Volatile • Non-Volatile Technologies: • EPROM (Obsolete) • EEPROM • Anti-Fuse • SRAM

  40. Summary Programming Elements

  41. I/O L I Generic FPLD Design At a minimum, every FPLD needs 1. Programmable Logic (L) 2. Programmable Interconnects (I) 3. Input/Output Logic (I/O) FPLD

  42. I/O L I Generic FPLD Design 1/3 Logic, 1/3 Interconnects, 1/3 Input/Output FPLD Do I have enough logic?

  43. Generic FPLD Design 1/2 Logic, 1/4 Interconnects, 1/4 Input/Output FPLD L I I/O Logic is good, but now do I have enough interconnects for my logic?

  44. Generic FPLD Design 1/4 Logic, 1/2 Interconnects, 1/4 Input/Output FPLD L I I/O Ok, I have enough interconnects for my logic. Do I have enough I/O?

  45. Generic FPLD Design Different vendors use different approaches FPLD L I I/O Let’s examine Altera MAX and Altera Flex!!!

  46. Altera Max-7000

  47. Altera MAX-7000 Device Family • EEPROM used as PE • Non-volatile and Re-programmable

  48. Definitions • Useable gates • Number of equivalent TTL NAND gates • Macrocells • Number of unique mini PALs • Maximum user I/O Pins • Tpd = Input to non-registered output • Tsu = External global clock register setup time • Tfsu = External fast input register setup time • Tco1 = Global clock to output delay • Fcnt (MHz) = Maximum 16 bit up/down counter freq

  49. MAX-7000S Block Diagram

  50. Block Diagram Notes • Global clocks • Global reset • Global Output Enable • Global Inputs • PIA - Programmable Interconnect Array • LABs – Logic Array Blocks • Macrocells are contained in LABs

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