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亂數產生器設計

亂數產生器設計. VHDL 數位電路實習與專題設計 文魁資訊 -UE301. 單元 7-1 號碼 0 ~ 9 之亂數產生器實習. 實驗目的 了解利用振盪頻率產生亂數變化的原理 按下彈跳按鍵產生不同數字並在七段顯示器顯示. 相關知識. 號碼 0 ~ 9 亂數產生器示意圖. 實驗功能. 以彈跳按鍵來控制亂數產生器的計數器之開始計數與停止計數 將亂數產生器的輸出顯示在七段顯示器上 按一次彈跳按鍵則開始計數，再按一次則停止計數. RANDOM_MODE9 系統規格表. 系統方塊圖. 0 ~ 9 的亂數產生器實習系統規格表. 實驗電路圖.

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亂數產生器設計

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  1. 亂數產生器設計 VHDL數位電路實習與專題設計 文魁資訊-UE301

  2. 單元7-1 號碼0 ~ 9之亂數產生器實習 • 實驗目的 • 了解利用振盪頻率產生亂數變化的原理 • 按下彈跳按鍵產生不同數字並在七段顯示器顯示 VHDL數位電路實習與專題設計

  3. 相關知識 號碼0 ~ 9亂數產生器示意圖 VHDL數位電路實習與專題設計

  4. 實驗功能 • 以彈跳按鍵來控制亂數產生器的計數器之開始計數與停止計數 • 將亂數產生器的輸出顯示在七段顯示器上 • 按一次彈跳按鍵則開始計數，再按一次則停止計數 RANDOM_MODE9系統規格表 VHDL數位電路實習與專題設計

  5. 系統方塊圖 0 ~ 9的亂數產生器實習系統規格表 VHDL數位電路實習與專題設計

  6. 實驗電路圖 VHDL數位電路實習與專題設計

  7. 1 ------------------------------------------------------------------ 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：clk_div.vhd 4 --功 能：除頻功能 5 --日 期：2003.8.8 6 ------------------------------------------------------------------ 7 library ieee; 8 use ieee.std_logic_1164.all; 9 use ieee.std_logic_unsigned.all; 10 use ieee.std_logic_arith.all; 11 12 entity clk_div is 13 generic(divisor:integer:=9); 14 port( 15 clk_in : in std_logic; 16 clk_out: out std_logic 17 ); 18 end clk_div; 19 20 architecture arch of clk_div is 21 signal cnt2 : std_logic; 22 begin 23 ---------- clk divider ---------- 24 process(clk_in) 25 variable cnt1 : integer range 0 to divisor:=1; 26 variable divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_in'event and clk_in='1') then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 34 cnt1 := cnt1 + 1; 35 end if; 36 end if; 37 ----- clk_out register clk generator 38 if (clk_in'event and clk_in='1') then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 40 cnt2 <= not cnt2 ; 41 end if; 42 end if; 43 clk_out <= cnt2 ; 44 end process; 45 end arch; 除頻器程式碼 VHDL數位電路實習與專題設計

  8. 1 -------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：random_mode9.vhd 4 --功 能：亂數產生號碼0~9 5 --日 期：2003.8.8 6 -------------------------------------------------------------- 7 library ieee; 8 use ieee.std_logic_1164.all; 9 10 entity random_mode9 is 11 port( 12 clk :in std_logic; 13 rst :in std_logic; 14 sel :in std_logic; 15 q:out std_logic_vector(3 downto 0) 16 ); 17 end random_mode9; 18 19 architecture a of random_mode9 is 20 type state_type is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9); 21 signal state: state_type; 22 signal qt: std_logic_vector(3 downto 0); 23 signal d, d0, d1: std_logic; 24 signal run : std_logic := '0'; 25 begin 26 process(clk) 27 begin 28 if rst = '0' then 29 state <= S0; 30 elsif clk'event and clk = '1' then 31 d1<=d0; d0<=sel; 32 case state is 33 when S0 => if (run = '0') then state <= S1; end if; 34 when S1 => if (run = '0') then state <= S2; end if; 35 when S2 => if (run = '0') then state <= S3; end if; 36 when S3 => if (run = '0') then state <= S4; end if; 37 when S4 => if (run = '0') then state <= S5; end if; 38 when S5 => if (run = '0') then state <= S6; end if; 39 when S6 => if (run = '0') then state <= S7; end if; 40 when S7 => if (run = '0') then state <= S8; end if; 41 when S8 => if (run = '0') then state <= S9; end if; 42 when S9 => if (run = '0') then state <= S0; end if; 43 when others => null; 44 end case; 45 end if; 46 end process; 47 d <= d1 and not d0; 號碼0 ~ 9亂數產生器程式碼 VHDL數位電路實習與專題設計

  9. 48 with state select 49 qt <= "0000" when S0, 50 "0001" when S1, 51 "0010" when S2, 52 "0011" when S3, 53 "0100" when S4, 54 "0101" when S5, 55 "0110" when S6, 56 "0111" when S7, 57 "1000" when S8, 58 "1001" when S9; 59 process(d, clk) 60 begin 61 if clk'event and clk='1' then 62 q<=qt; 63 if (d='1') then 64 run <= not run; 65 end if; 66 end if; 67 end process; 68 end a; 號碼0 ~ 9亂數產生器程式碼 VHDL數位電路實習與專題設計

  10. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：bin2dec.vhd 4 --功 能：二進制轉七段顯示器編碼 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 -- a <= seg(0); 8 -- b <= seg(1); 9 -- c <= seg(2); 10 -- d <= seg(3); 11 -- e <= seg(4); 12 -- f <= seg(5); 13 -- g <= seg(6); 14 library ieee; 15 use ieee.std_logic_1164.all; 16 entity bin2dec is 17 port ( 18 dip : in std_logic_vector(3 downto 0); 19 seg : out std_logic_vector(6 downto 0); 20 seg_en : out std_logic 21 ); 22 end bin2dec; 23 24 architecture arch of bin2dec is 25 begin 26 ----- PROGRAM BODY ----- 27 seg_en<='1'; 28 ----- binary to seven segment decoder ----- 29 process (dip) 30 begin 31 case dip is 32 when "0000" => seg <= "1000000"; -- 0 33 when "0001" => seg <= "1111001"; -- 1 34 when "0010" => seg <= "0100100"; -- 2 35 when "0011" => seg <= "0110000"; -- 3 36 when "0100" => seg <= "0011001"; -- 4 37 when "0101" => seg <= "0010010"; -- 5 38 when "0110" => seg <= "0000010"; -- 6 39 when "0111" => seg <= "1111000"; -- 7 40 when "1000" => seg <= "0000000"; -- 8 41 when "1001" => seg <= "0010000"; -- 9 42 when "1010" => seg <= "0001000"; -- A 43 when "1011" => seg <= "0000011"; -- b 44 when "1100" => seg <= "1000110"; -- C 45 when "1101" => seg <= "0100001"; -- d 46 when "1110" => seg <= "0000110"; -- E 47 when "1111" => seg <= "0001110"; -- F 48 when others => seg <= "1111111"; 49 end case; 50 end process; 51 end arch; 二進制轉七段顯示器編碼程式碼 VHDL數位電路實習與專題設計

  11. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：random9_top.vhd 4 --功 能：以彈跳按鍵產生亂數0~9且在七段顯示器顯示 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 library ieee; 8 use ieee.std_logic_1164.all; 9 use ieee.std_logic_unsigned.all; 10 use ieee.std_logic_arith.all; 11 12 entity random9_top is 13 port( 14 clk: in std_logic; 15 rst: in std_logic; 16 sel: in std_logic; 17 seg_out: out std_logic_vector(6 downto 0); 18 seg_one_en: out std_logic; 19 seg_ten_en: out std_logic; 20 bz : out std_logic 21 ); 22 end random9_top; 23 24 architecture arch of random9_top is 25 ----- clk_div ----- 26 component clk_div 27 generic(divisor:integer:=8); 28 port( 29 clk_in : in std_logic; 30 clk_out: out std_logic 31 ); 32 end component; 33 ----- bin2dec ----- 34 component bin2dec 35 port( 36 dip : in std_logic_vector(3 downto 0); 37 seg : out std_logic_vector(6 downto 0); 38 seg_en : out std_logic 39 ); 40 end component; 41 ----- random_mode9 ----- 42 component random_mode9 43 port( 44 clk : in std_logic; 45 rst : in std_logic; 46 sel : in std_logic; 47 q : out std_logic_vector(3 downto 0) 48 ); 49 end component; 50 signal clk1: std_logic; 51 signal dip : std_logic_vector(3 downto 0); 52 begin 53 seg_ten_en <= '0'; 54 bz <= '0'; 55 U1: clk_div 56 generic map(184320) 57 port map(clk,clk1); 58 U2: random_mode9 port map(clk1,rst,sel,dip); 59 U3: bin2dec port map(dip,seg_out,seg_one_en); 60 end arch; 亂數產生器主程式 VHDL數位電路實習與專題設計

  12. 主程式電路連線(random9_top_grahp.gdf) 註：在主程式中加入蜂鳴器控制信號，是為了不讓蜂鳴器因為信號干擾而發出聲響， 因此我們將蜂鳴器控制信號bz設定為低電位。 VHDL數位電路實習與專題設計

  13. 功能模擬 VHDL數位電路實習與專題設計

  14. 腳位配置 號碼0 ~ 9之亂數產生器實習腳位配置表 VHDL數位電路實習與專題設計

  15. 編譯錯誤解決方法 編繹錯誤訊息圖 編繹錯誤訊息圖 VHDL數位電路實習與專題設計

  16. 編譯錯誤解決方法 將Clear的設定取消圖 設定Global Project Logic Synthesis圖 VHDL數位電路實習與專題設計

  17. 編譯錯誤解決方法 重新Compiler VHDL數位電路實習與專題設計

  18. 7 Segment RST SEL FPT-3實驗板元件規劃 VHDL數位電路實習與專題設計

  19. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：clk_div_lp2900.vhd 4 --功 能：除頻功能, clk_out = clk_in / divisor 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 library ieee; 8 use ieee.std_logic_1164.all; 9 use ieee.std_logic_unsigned.all; 10 use ieee.std_logic_arith.all; 11 12 entity clk_div_lp2900 is 13 generic(divisor:integer:=1000000); 14 port( 15 clk_in : in std_logic; 16 clk_out: out std_logic 17 ); 18 end clk_div_lp2900; 19 20 architecture arch of clk_div_lp2900 is 21 signal cnt2 : std_logic; 22 begin 23 ---------- clk divider ---------- 24 process(clk_in) 25 variable cnt1 : integer range 0 to divisor:=1; 26 variable divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_in'event and clk_in='1') then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 34 cnt1 := cnt1 + 1; 35 end if; 36 end if; 37 ----- clk_out register clk generator ----- 38 if (clk_in'event and clk_in='1') then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 40 cnt2 <= not cnt2 ; 41 end if; 42 end if; 43 clk_out <= cnt2 ; 44 end process; 45 end arch; 用於LP-2900實驗板上的除頻器程式碼 VHDL數位電路實習與專題設計

  20. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：bin2dec_LP2900.vhd 4 --功 能：二進制轉七段顯示器編碼 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 -- a <= seg(0); 8 -- b <= seg(1); 9 -- c <= seg(2); 10 -- d <= seg(3); 11 -- e <= seg(4); 12 -- f <= seg(5); 13 -- g <= seg(6); 14 15 library ieee; 16 use ieee.std_logic_1164.all; 17 entity bin2dec_LP2900 is 18 port ( 19 dip : in std_logic_vector(3 downto 0); 20 seg : out std_logic_vector(6 downto 0); 21 DE : out std_logic_vector(2 downto 0) 22 ); 23 end bin2dec_LP2900; 24 25 architecture arch of bin2dec_LP2900 is 26 begin 27 ----- PROGRAM BODY ----- 28 DE<="000"; 29 ----- binary to seven segment decoder ----- 30 process (dip) 31 begin 32 case dip is 33 when "0000" => seg <= "0111111"; -- 0 34 when "0001" => seg <= "0000110"; -- 1 35 when "0010" => seg <= "1011011"; -- 2 36 when "0011" => seg <= "1001111"; -- 3 37 when "0100" => seg <= "1100110"; -- 4 38 when "0101" => seg <= "1101101"; -- 5 39 when "0110" => seg <= "1111101"; -- 6 40 when "0111" => seg <= "0000111"; -- 7 41 when "1000" => seg <= "1111111"; -- 8 42 when "1001" => seg <= "1101111"; -- 9 43 when "1010" => seg <= "1110111"; -- A 44 when "1011" => seg <= "1111100"; -- b 45 when "1100" => seg <= "0111001"; -- C 46 when "1101" => seg <= "1011110"; -- d 47 when "1110" => seg <= "1111001"; -- E 48 when "1111" => seg <= "1110001"; -- F 49 when others => seg <= "0000000"; 50 end case; 51 end process; 52 end arch; 用於LP-2900實驗板上的二進制轉七段顯示器編碼程式碼 VHDL數位電路實習與專題設計

  21. 主程式電路架構圖(random9_lp2900.gdf) VHDL數位電路實習與專題設計

  22. 腳位配置表（LP-2900實驗板） VHDL數位電路實習與專題設計

  23. 7 segment RST SEL LP-2900實驗板元件規劃 VHDL數位電路實習與專題設計

  24. 練習 • 試著設計出一個以彈跳按鍵控制的1 ~ 8亂數產生器，並將結果在LED上顯示。 • 試著設計出一個以彈跳按鍵控制的亂數產生器，並可先以指撥開關設定一數字並顯示在十位數七段顯示器上，若所產生的亂數與指撥開關所設定的數字相同時，啟動蜂鳴器。 VHDL數位電路實習與專題設計

  25. 單元7-2樂透彩亂數產生器實習 • 實驗目的 • 利用亂數產生器產生1 ~ 42 的樂透彩號碼。 • 按下彈跳按鍵產生樂透彩號碼並在七段顯示器顯示。 VHDL數位電路實習與專題設計

  26. 相關知識 • 當十位數是0的情況下，個位數計數器需要從1開始計數到9。 • 當十位數是4的情況下，個位數計數器需要從0開始計數到2。 • 當十位數是4的情況下，且個位數計數器為2，則必須由01開始重新計數。 樂透彩亂數產生器示意圖 VHDL數位電路實習與專題設計

  27. 實驗功能 • 以彈跳按鍵作為產生號碼的控制訊號，將1 ~ 42號的亂數產生器所產生出來的十位數與個位數分別以SCAN的方式在七段顯示器上顯示出來。 RANDOM_LOTTO系統規格表 VHDL數位電路實習與專題設計

  28. 樂透彩亂數產生器實習 樂透彩亂數產生器示意圖 樂透彩亂數產生器系統規格表 VHDL數位電路實習與專題設計

  29. 實驗電路圖 VHDL數位電路實習與專題設計

  30. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：clk_gen.vhd 4 --功 能：頻率產生器 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 library ieee; 8 use ieee.std_logic_1164.all; 9 use ieee.std_logic_unsigned.all; 10 entity clk_gen is 11 port( 12 clk_in : in std_logic; 13 clk_out1: out std_logic; 14 clk_out2: out std_logic 15 ); 16 end clk_gen; 17 architecture a of clk_gen is 18 signal cnt : std_logic_vector(19 downto 0); 19 signal reset: std_logic; 20 begin 21 process (clk_in) 22 begin 23 if reset='1' then 24 cnt<="00000000000000000000"; 25 elsif clk_in'event and clk_in='1' then 26 cnt<=cnt+1; 27 end if; 28 end process; 29 30 reset<='1' when cnt=921599 else '0'; 31 clk_out1<=cnt(14); --32hz 32 clk_out2<=cnt(13); --64hz 33 end a; 頻率產生器程式碼 VHDL數位電路實習與專題設計

  31. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：random_lotto.vhd 4 --功 能：亂數產生號碼1~42 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 library ieee; 8 use ieee.std_logic_1164.all; 9 use ieee.std_logic_arith.all; 10 use ieee.std_logic_unsigned.all; 11 12 entity random_lotto is 13 port( 14 clk : in std_logic; 15 rst : in std_logic; 16 sel : in std_logic; 17 q_one: out std_logic_vector(3 downto 0); 18 q_ten: out std_logic_vector(3 downto 0) 19 ); 20 end random_lotto; 21 22 architecture a of random_lotto is 23 signal cnt_one,cnt_ten : std_logic_vector(3 downto 0); 24 signal s,s0,s1 : std_logic; 25 begin 26 process (clk,rst) 27 begin 28 if rst='0' then 29 cnt_one <= "0001"; 30 cnt_ten <= "0000"; 31 s0 <= '1'; s1 <= '1'; 32 elsif clk'event and clk='1' then 33 s1<=s0; s0<=sel; 34 if cnt_ten = "0100" then --40 35 if cnt_one = "0010" then 36 cnt_one <= "0001"; --1 37 cnt_ten <= "0000"; 38 else 39 cnt_one <= cnt_one + 1; 40 end if; 41 elsif cnt_one = "1001" then 42 cnt_one <= "0000"; 43 cnt_ten <= cnt_ten + 1; 44 else 45 cnt_one <= cnt_one + 1; 46 end if; 47 end if; 48 end process; 49 s <= s1 and not s0; 50 process(clk,rst) 51 begin 52 if clk'event and clk='1' then 53 if rst='0' then 54 q_one <= "0000"; 55 q_ten <= "0000"; 56 elsif s = '1' then 57 q_one <= cnt_one; 58 q_ten <= cnt_ten; 59 end if; 60 end if; 61 end process; 62 end a; 樂透彩亂數產生器程式碼 VHDL數位電路實習與專題設計

  32. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：bin2seg0_scan.vhd 4 --功 能：具掃描功能之二進制轉七段顯示器編碼 5 ------------------------------------------------------------------- 6 --a <= seg(0); b <= seg(1); c <= seg(2); d <= seg(3); 7 --e <= seg(4); f <= seg(5); g <= seg(6); 8 library ieee; 9 use ieee.std_logic_1164.all; 10 use ieee.std_logic_unsigned.all; 11 use ieee.std_logic_arith.all; 12 13 entity bin2seg0_scan is 14 port ( 15 clk: in std_logic; 16 seg_en: in std_logic; 17 q_one: in std_logic_vector(3 downto 0); 18 q_ten : in std_logic_vector(3 downto 0); 19 seg_out : out std_logic_vector(6 downto 0); 20 seg_one_en: out std_logic; 21 seg_ten_en: out std_logic 22 ); 23 end bin2seg0_scan; 24 25 architecture arch of bin2seg0_scan is 26 signal bin: std_logic_vector(3 downto 0); 27 signal seg: std_logic_vector(6 downto 0); 28 signal sel: integer range 0 to 1; 29 begin 30 ----- scan and signal assign ----- 31 process (clk, seg_en) 32 begin 33 if clk'event and clk='1' then 34 if (seg_en='0') then 35 seg_one_en<='0'; 36 seg_ten_en<='0'; 37 sel<=0; 38 else 39 sel<=sel+1; 40 case sel is 41 when 0 => 42 bin<=q_one; 43 seg_one_en<='1'; 44 seg_ten_en<='0'; 45 when 1 => 46 bin<=q_ten; 47 seg_one_en<='0'; 48 seg_ten_en<='1'; 49 when others => 50 null; 51 end case; 52 end if; 53 end if; 54 end process; 具掃描功能之二進制轉七段顯示器編碼程式碼 VHDL數位電路實習與專題設計

  33. 55 ----- binary to seven segment decoder ----- 56 process (bin) 57 begin 58 case bin is 59 when "0000" => seg_out <= "1000000"; -- 0 60 when "0001" => seg_out <= "1111001"; -- 1 61 when "0010" => seg_out <= "0100100"; -- 2 62 when "0011" => seg_out <= "0110000"; -- 3 63 when "0100" => seg_out <= "0011001"; -- 4 64 when "0101" => seg_out <= "0010010"; -- 5 65 when "0110" => seg_out <= "0000010"; -- 6 66 when "0111" => seg_out <= "1111000"; -- 7 67 when "1000" => seg_out <= "0000000"; -- 8 68 when "1001" => seg_out <= "0010000"; -- 9 69 when others => seg_out <= "1111111"; 70 end case; 71 end process; 72 end arch; 具掃描功能之二進制轉七段顯示器編碼程式碼 VHDL數位電路實習與專題設計

  34. 1 ------------------------------------------------------------------- 2 --實驗名稱：亂數產生器實習 3 --檔案名稱：random_lotto_top.vhd 4 --功 能：樂透彩亂數產生器 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 library ieee; 8 use ieee.std_logic_1164.all; 9 use ieee.std_logic_unsigned.all; 10 use ieee.std_logic_arith.all; 11 12 entity random_lotto_top is 13 port( 14 clk : in std_logic; 15 rst : in std_logic; 16 sel : in std_logic; 17 seg_en : in std_logic; 18 seg_out : out std_logic_vector(6 downto 0); 19 seg_one_en: out std_logic; 20 seg_ten_en: out std_logic; 21 bz : out std_logic 22 ); 23 end random_lotto_top; 24 25 architecture arch of random_lotto_top is 26 ----- random_lotto ----- 27 component random_lotto 28 port( 29 clk : in std_logic; 30 rst : in std_logic; 31 sel : in std_logic; 32 q_one: out std_logic_vector(3 downto 0); 33 q_ten: out std_logic_vector(3 downto 0) 34 ); 35 end component; 36 ----- bin2seg0_scan ----- 37 component bin2seg0_scan 38 port ( 39 clk : in std_logic; 40 seg_en : in std_logic; 41 q_one : in std_logic_vector(3 downto 0); 42 q_ten : in std_logic_vector(3 downto 0); 43 seg_out : out std_logic_vector(6 downto 0); 44 seg_one_en: out std_logic; 45 seg_ten_en: out std_logic 46 ); 47 end component; 48 ----- clk_gen ----- 49 component clk_gen 50 port( 51 clk_in : in std_logic; 52 clk_out1: out std_logic; 53 clk_out2: out std_logic 54 ); 55 end component; 56 signal clk_out1,clk_out2 : std_logic; 57 signal q_one,q_ten : std_logic_vector(3 downto 0); 58 signal clk_64 : std_logic; 59 begin 60 bz<=’0’; 61 U1: clk_gen port map(clk,clk_out1,clk_out2); 62 U2: random_lotto port map(clk_out1,rst,sel,q_one,q_ten); 63 U3: bin2seg0_scan port map(clk_out2, seg_en, q_one, q_ten, seg_out, 64 seg_one_en, seg_ten_en); 65 end arch; 樂透彩亂數產生器主程式 VHDL數位電路實習與專題設計

  35. 功能模擬 樂透彩亂數產生器random_lotto功能模擬圖 VHDL數位電路實習與專題設計

  36. 樂透彩亂數產生器實習腳位配置表 VHDL數位電路實習與專題設計

  37. 7 Segment RST SEL SEG_EN FPT-3實驗板元件規劃 VHDL數位電路實習與專題設計

  38. 1 ------------------------------------------------------------------- 2 --實驗名稱：樂透彩亂數產生器實習 3 --檔案名稱：clk_div_64_lp2900.vhd 4 --功 能：產生掃描頻率 5 --日 期：2003.8.8 6 ------------------------------------------------------------------- 7 Library IEEE; 8 Use IEEE.std_logic_1164.all; 9 Use ieee.std_logic_unsigned.all; 10 Use IEEE.std_logic_arith.all; 11 12 Entity clk_div_64_lp2900 is 13 Port( 14 clk: in std_logic; --system clock(10MHz) 15 clk_64hz: out std_logic; --64Hz output 16 clk_32hz: out std_logic --32Hz outpout 17 ); 18 end clk_div_64_lp2900; 19 architecture arch of clk_div_64_lp2900 is 20 signal count : integer range 0 to 156250; 21 signal clk_64_temp,clk_32_temp : std_logic; 22 begin 23 process (clk) 24 begin 25 if rising_edge(clk) then 26 count<=count+1; 27 if count>=78124 then 28 clk_64_temp <= '1'; 29 else 30 clk_64_temp <= '0'; 31 end if; 32 end if; 33 clk_64hz <= clk_64_temp; 34 end process; 35 36 process(clk_64_temp) 37 begin 38 if rising_edge(clk_64_temp) then 39 clk_32_temp <= not clk_32_temp; 40 end if; 41 clk_32hz <= clk_32_temp; 42 end process; 43 end arch; 除頻電路程式碼 (LP-2900) VHDL數位電路實習與專題設計

  39. 1 -------------------------------------------------------------------- 2 --實驗名稱：樂透彩亂數產生器實習 3 --檔案名稱：bin2seg_scan_lp2900.vhd 4 --功 能：具掃描功能之二進制轉七段顯示器編碼 5 --日 期：2003.8.8 (LP-2900) 6 ------------------------------------------------------------------- 7 --a <= seg(0); b <= seg(1); c <= seg(2); d <= seg(3); 8 --e <= seg(4); f <= seg(5); g <= seg(6); 9 library ieee; 10 use ieee.std_logic_1164.all; 11 use ieee.std_logic_unsigned.all; 12 use ieee.std_logic_arith.all; 13 14 entity bin2seg_scan_lp2900 is 15 port ( 16 clk : in std_logic; 17 seg_en : in std_logic; 18 q_one : in std_logic_vector(3 downto 0); 19 q_ten : in std_logic_vector(3 downto 0); 20 seg_out : out std_logic_vector(6 downto 0); 21 DE : out std_logic_vector(2 downto 0) 22 ); 23 end bin2seg_scan_lp2900; 24 25 architecture arch of bin2seg_scan_lp2900 is 26 signal bin: std_logic_vector(3 downto 0); 27 signal seg: std_logic_vector(6 downto 0); 28 signal sel: integer range 0 to 1; 29 begin 30 ----- scan and signal assign ----- 31 process (clk, seg_en) 32 begin 33 if clk'event and clk='1' then 34 if (seg_en='0') then 35 sel<=0; 36 else 37 sel<=sel+1; 38 case sel is 39 when 0 => 40 bin<=q_one; 41 DE <= "101"; 42 when 1 => 43 bin<=q_ten; 44 DE <= "100"; 45 when others => 46 null; 47 end case; 48 end if; 49 end if; 50 end process; 具掃描功能之二進制轉七段顯示器編碼程式碼(LP-2900) VHDL數位電路實習與專題設計

  40. 51 ----- binary to seven segment decoder ----- 52 process (bin) 53 begin 54 case bin is 55 when "0000" => seg_out <= "0111111"; -- 0 56 when "0001" => seg_out <= "0000110"; -- 1 57 when "0010" => seg_out <= "1011011"; -- 2 58 when "0011" => seg_out <= "1001111"; -- 3 59 when "0100" => seg_out <= "1100110"; -- 4 60 when "0101" => seg_out <= "1101101"; -- 5 61 when "0110" => seg_out <= "1111101"; -- 6 62 when "0111" => seg_out <= "0000111"; -- 7 63 when "1000" => seg_out <= "1111111"; -- 8 64 when "1001" => seg_out <= "1101111"; -- 9 65 when others => seg_out <= "0000000"; 66 end case; 67 end process; 68 end arch; 具掃描功能之二進制轉七段顯示器編碼程式碼(LP-2900) VHDL數位電路實習與專題設計

  41. 主程式電路架構圖(random_lotto_top_LP2900.gdf) VHDL數位電路實習與專題設計

  42. 樂透彩亂數產生器實習腳位規劃表（LP-2900實驗板） VHDL數位電路實習與專題設計

  43. 7 segment RST SEL LP-2900實驗板元件規劃 VHDL數位電路實習與專題設計

  44. 練習 • 試著在LP-2900上設計一個4星彩號碼產生機，也就是隨機產生4個0~9的數字。 • 試著在LP-2900上設計一個對對樂號碼產生機，也就是隨機產生6個0~9的數字。 VHDL數位電路實習與專題設計

  45. 勘誤 VHDL數位電路實習與專題設計

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