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ベル研出張報告

ベル研出張報告. 木下　基 稲田　智志. 出張目的. ２セクション分割型半導体レーザーの作成. エタロンフィルター用半導体レーザーの作成. これらについて …. 設計のためのノウハウを得る. 結晶成長＆プロセスを行う. 共同研究者との親善. 観光. 語学力向上. Map. Murray Hill. Crawford Hill. Crawford Hill. 正面玄関. 裏山から. ！？. ホーンリフレクタアンテナ. 埋め込み型半導体レーザーの作成. 1.3μm ＬＤ. Q1.3. Q1.1. Q1.1. Grow successive

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ベル研出張報告

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  1. ベル研出張報告 木下　基 稲田　智志

  2. 出張目的 ２セクション分割型半導体レーザーの作成 エタロンフィルター用半導体レーザーの作成 これらについて… 設計のためのノウハウを得る 結晶成長＆プロセスを行う 共同研究者との親善 観光 語学力向上

  3. Map Murray Hill Crawford Hill

  4. Crawford Hill 正面玄関 裏山から ！？ ホーンリフレクタアンテナ

  5. 埋め込み型半導体レーザーの作成

  6. 1.3μmＬＤ Q1.3 Q1.1 Q1.1 Grow successive n-InP, n-InGaAsP, p-InP on substrate by MOCVD. p+-InP p+-InGaAs 20nm 酸化防止のため 50nm 金属とのcontactのため p+-InP u-InP 800nm 25nm InGaAsP n-InP 150nm n-InP(sub) 25nm

  7. Remove p+-InGaAs, p+-InP layers with HCl. p+-InP p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

  8. p+-InGaAs Deposit SiO2. SiO2(120nm) p+-InP u-InP InGaAsP n-InP n-InP(sub)

  9. p+-InGaAs Spin-coat p-resist. Pre-bakethe resist. resist SiO2 p+-InP u-InP InGaAsP n-InP n-InP(sub)

  10. p+-InGaAs Exposure mask resist SiO2 p+-InP u-InP InGaAsP n-InP n-InP(sub)

  11. p+-InGaAs Develop resist SiO2 p+-InP u-InP InGaAsP n-InP n-InP(sub)

  12. p+-InGaAs Rinse & post bake resist SiO2 p+-InP u-InP InGaAsP n-InP n-InP(sub)

  13. p+-InGaAs Remove SiO2 with HF resist SiO2 p+-InP u-InP InGaAsP n-InP n-InP(sub)

  14. p+-InGaAs Remove resist. Form SiO2 stripes. SiO2 p+-InP u-InP InGaAsP n-InP n-InP(sub)

  15. Deep Etching with HBr:HCl:HAc:H2O2 SiO2 p+-InGaAs u-InP p+-InP InGaAsP n-InP n-InP(sub)

  16. Deep Etching with HBr:HCl:HAc:H2O2 SiO2 p+-InGaAs u-InP p+-InP 実際に再成長させる厚さ InGaAsP n-InP n-InP(sub)

  17. Regrow iron doped InP and n-InP layor on the wafer. SiO2 n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  18. Remove SiO2 with pure HF. SiO2 n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  19. Remove InGaAs with H2SO4:H2O:H2O2. n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  20. regrow p++-InP layer ドープするZnの濃度を徐々に増やしていく。 n-InP p++-InP(2μm) i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  21. regrow p+-InGaAs and p+-InP layers p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  22. Paste p-resist. resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  23. Exposure mask resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  24. Develop resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  25. Deep etching to make trenches. resist p+-InP p+-InGaAs P-InP層のseparate n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  26. Remove resist. p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  27. Deposit SiO2 p+-InP SiO2（540nm） p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  28. Paste p-resist resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  29. Exposure mask resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  30. Develop resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  31. Remove SiO2 with HF resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  32. Remove InP with HCl. resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  33. Evaporate 1st-metal. 1st-metal(410nm) resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  34. Remove resist (lift-off). 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  35. Remove resist (lift-off). 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  36. Put n-resist. resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  37. Exposure mask resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  38. Develop resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  39. Develop resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  40. Evaporate 2nd-metal. 2nd-metal(860nm) resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  41. Remove resist. (Lift-Off) 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  42. Lift-Off 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  43. Thinningto 200μm 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  44. Thinning 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

  45. Evaporate n-electrode 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP metal(560nm) n-InP(sub)

  46. 完成！ p-electrode p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-electrode n-InP(sub)

  47. ＬＤ 900μm 900μm 300μm 300μm

  48. ＱＷＬＤ 900μm 900μm 300μm 300μm

  49. Ｉ－Ｌ特性* Ｉ－Ｖ特性* 発振スペクトル* *いずれもQWLD、300mm

  50. ２セクション分割型半導体レーザー

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