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LHCb Calorimeter Front-End Upgrade: Signal Shape Optimization and ICECAL Integration

This project involves enhancing the front-end electronics of the LHCb calorimeter through Signal Shape optimization and ICECAL integration. The upgrade includes Signal Shape simulations, Pole-Zero filtering, and integrator Pole-Zero Compensation techniques. Additionally, FPGA Correction methods are explored to improve signal processing. The goal is to reduce signal distortion and improve signal processing efficiency for better data analysis.

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LHCb Calorimeter Front-End Upgrade: Signal Shape Optimization and ICECAL Integration

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  1. TB 2012: Signal Shape and ICECAL Upgrade of the front end electronics of the LHCb calorimeter E. Picatoste Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB Calo Upgrade Test Beam Data Analysis Meeting – December 3rd 2012

  2. Outline • Signal Shapes • ICECAL integrator simulations • Pole-zero filtering LHCb Upgrade

  3. Signal Shapes 3

  4. Simulations: Plateau • Plateau for different Rf: • ASIC Rf=13.7 KOhm • Use Anatoli’s wave form • Scan different phases 4

  5. Simulations: Plateau • Plateau for different Rf: • Lower Rf offer better plateau • Always less than 4ns • Use TB2012 clipped shape • Scan different phases 5

  6. Simulations: Tail Effect • Anatoli’s shape • Same data from the plateau test • Optimal phase ~10ns • Study the following output values after the main signal (V0): • V1/V0 ~11% • V2/V0 ~1.5% V1/V0 ~11% V2/V0 ~1.5% 6

  7. Simulations: Tail Effect • TB2012 clipped shape • Same data from the plateau test • Optimal phase ~-9ns • Study the following output values after the main signal (V0): • V1/V0 ~10% • V2/V0 ~1.5% V1/V0 ~10% V2/V0 ~1.5% 7

  8. Pole-Zero Compensation R1 R2 C • The effect of the tail of the signal can be reduced with a pole-zero filter 8

  9. Integrator Pole-Zero Compensation R C1 C2 • The effect of the tail of the signal can be reduced with a pole-zero filter • Adapt the idea to the integrator • To be studied in simulations. 9

  10. FPGA Correction • FPGA correction in two steps: • Pedestal subtraction: minimum of the 2 previous samples of the same subchannel. • Cable correction subtraction • Cable correction subtraction proposal with shift registers and adders to be studied (~binary weighted coding) 10

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