SABA ZIA 2007-NUST-MS-PHD-TE-05

1. PERFORMANCE COMPARISON AND EVALUATION OF 802.11A AND ITS IMPLEMENTATION IN RECONFIGURABLE ENVIRONMENT Project Advisor: Dr. N. D Gohar (HOD CSE, SEECS, NUST) Committee Members: Mr. Imtiaz Khokhar (Asst. Prof, EE, MCS, NUST) Dr. Adnan Khan (Asst. Prof, EE, MCS, NUST) Mr. Bilal Saqib (lecturer, CSE, SEECS, NUST) SABA ZIA 2007-NUST-MS-PHD-TE-05

2. Outline • Introduction • SDR, OFDM based standards, WLAN • Reconfigurable Environment • Performance Evaluation in a Reconfigurable Environment • Reconfigurable Kernels • Implementation Overview • Kernel Algorithm • Kernel Simulation Results • Kernel Synthesis: Max Frequency, Area requirements • Simulated and Synthesized Example • WLAN PHY (802.11a)

3. Introduction

4. RF Front End Receive Radio Frequency (RF) Analog to Digital Conversion (A/D) Baseband Processing Transmit Control (Parameterization) Introduction • Performance Comparison and Evaluation of 802.11a and its Implementation in a Reconfigurable Environment • Software Defined Radio Development using a Network-On-Chip based Rapid Prototyping Platform

5. Physical Layer Architecture and Kernel Identification (802.11a) 5 Ref: IEEE Std 802.11a-1999(R2003)

6. Physical Layer Architecture and Kernel Identification Data Scrambler/ Descrambler Convolutional Encoder / Viterbi decoder Puncturing / De-puncturing Data interleaver/ De-interleaver Subcarrier Modulation Mapping/ De-mapping Point Arrangement OFDM modulation IFFT/FFT Bit Reversal Guard interval insertion/ Removal 6

7. Individual Properties of each KernelData Scrambler/Descrambler • S (x)=x7 +x4 +1 Ref: IEEE Std 802.11a-1999(R2003) 7

8. Individual Properties of each KernelConvolutional Encoder/ Viterbi Decoder R = ½, 2/3 , ¾ For R= 1/2, G0=1338 G1 = 1718 Decoding by Viterbi Algorithm Ref: IEEE Std 802.11a-1999(R2003) 8

9. Individual Properties of each KernelPuncturing/De-puncturing Patterns Ref: IEEE Std 802.11a-1999(R2003) 9

10. Individual Properties of each KernelData Interleaver/ De-interleaver • Block size corresponding to the number of bits in a single OFDM symbol, NCBPS • Two-step permutation • i = (NCBPS/16) (k mod 16) + floor(k/16) where k = 0,1,…,NCBPS – 1 • j = s × floor (i/ s) + (i + NCBPS – floor(16 × i/NCBPS)) mod s where i = 0,1,… NCBPS – 1 • The value of s is determined by the number of coded bits per subcarrier, NBPSC, according to s = max(NBPSC/2,1) 10

11. Individual Properties of each KernelSubcarrier Modulation Mapping • BPSK,QPSK,16 QAM or 64 QAM depending on the rate requested • Gray coded constellation mappings • Resultant, d = (I + jQ) X KMOD Ref: IEEE Std 802.11a-1999(R2003) 11

12. Individual Properties of each KernelOFDM modulation (IFFT) • Divide the complex number string into groups of 48 complex numbers. Each such group will be associated with one OFDM symbol. • Each complex number is mapped into OFDM subcarriers numbered –26 to –22, –20 to –8, –6 to –1, 1 to 6, 8 to 20, and 22 to 26. • The “0” subcarrier, associated with center frequency, is omitted and filled with zero value. • Four subcarriers are inserted as pilots into positions –21, –7, 7, and 21. The total number of the subcarriers is 52 (48 + 4). • For each group of subcarriers –26 to 26, convert the subcarriers to time domain using inverse Fourier transform 12

13. Individual Properties of each KernelOFDM modulation (FFT-DIT) -1 -1 -1 -1 j j W0 -j -j W1 Time Domain Samples Frequency Domain Outputs -1 -1 W2 W3 W4 W5 W6 W7 Ref: IEEE Std 802.11a-1999(R2003) 13

14. Individual Properties of each KernelGuard Interval Insertion • Prepend to the Fourier-transformed waveform a circular extension of itself thus forming a GI, and truncate the resulting periodic waveform to a single OFDM symbol length by applying time domain windowing. Ref: IEEE Std 802.11a-1999(R2003) 14

15. Rate Dependent Parameters Ref: IEEE Std 802.11a-1999(R2003) 15

16. Reconfigurable Environment 16

17. Reconfigurable Environment System on Chip (SoC) Putting all the functions of a complete system (processor, memory, analog functions, external interfaces, timers, counters, voltage regulators, etc.) all on a single silicon chip, enabling the chip to operate as a standalone system 17

18. Communication Structures in System-on-Chip Memory Memory µP Memory RF µP RF µP RF Keyboard DSP DSP Keyboard DSP Keyboard Bus based Architecture Point to Point Links Network based Connections 18

19. Reconfigurable Environment Network on Chip (NOC) Resource Resource Resource RNI Router or Switch Resource Resource Resource Resource Resource Resource 19

20. Reconfigurable Kernels • Algorithmic size functionality • Reused across several standards • Combined Spatially or Temporally for bigger dimension • Fulfills overall performance constraints of multiple standards 20

21. SDR supporting OFDM based wireless Standards 21

22. Role of Kernel and 802.11a in SDR • 802.11a is an OFDM based standard • Each individual block of the 802.11a at physical layer will serve the functionality of the basic kernel of OFDM block • Kernel would be expanded spatially or temporally • Implementation allows reconfiguration to meet the constraints of other wireless standards

23. Performance Evaluation in Reconfigurable Environment • Size • Performance • Cost • Power

24. WLAN TX Controller • Initialization signals for datapath • Scrambler • Convolutional Encoder • Interleaver • Modulation Mapper • Point Arrange • FFT • Bit Reversal • Guard Insertion • State Machine • Short Preamble • Long Preamble • Header • Data • Initialization Signals for Controller WLAN TX CONTROLLER WLAN TX DATAPATH 24

25. Simulated and Synthesized Datapath IEEE STD 802.11a 25

26. Synthesis ResultsScrambler Scrambler clk rst dout din start

27. Simulation ResultsScrambler/ Descrambler

28. Synthesis ResultsConvolutional Encoder clk dout clk Start puncture Punc_en din rst Encoding Encoding start Puncturing rst clk out dout rate Puncturing Start puncture rst

29. Synthesis ResultsConvolutional Encoder

30. Simulation ResultsConvolutional Encoder with Puncturing

31. Synthesis ResultsInterleaver Ncbps Ncbps Addrb_0 Addra_0 Change Ncbps Change Ncbps Addrb_1 Addra_1 clk Permuted data1_0 clk Permuted data1_0 Permute d data_2 Serial_in Permuted data1_1 Permuted data1_1 Start First Permutation Start Second Permutation addra addra • douta douta addrb addrb clk clk dinb dinb

32. Synthesis ResultsInterleaver

33. Simulation Results Interleaver

34. Simulation ResultsInterleaver

35. Synthesis ResultsModulation Mapper addr dout clk Data_from_mem_bpsk Real_data Data_from_mem_qpsk addr addr addr Imaginary_data dout dout dout Data_from_mem_16QAM clk Data_from_mem_64QAM clk clk Mem_addr_bpsk Modulation Mem_addr_qpsk Qpsk_input Mem_addr_16QAM Bpsk_input Mem_addr_64QAM 16QAM_input 64QAM_input clk rst Start

36. Synthesis ResultsModulation Mapper

37. Simulation ResultsModulation Mapper

38. FFT-DIF State Machine

39. Synthesis ResultsFFT-DIF Dual Port RAM Port A Stage and Butterfly Controller + Data Memory Controller + Twiddle MemoryController Dual Port RAM Port B Radix-2 Cell Wnk WnkFactor LUT -1

40. Comparison of Synthesis ResultsFFT-DIF Ref: M. Ali Shami, A Hemani “Morphable datapath Unit: Smart and efficient datapath for Signal Processing Applications”, 2008

41. Simulation ResultsFFT-DIF

42. Simulation ResultsFFT-DIF

43. Simulated and Synthesized Controller IEEE STD 802.11a

45. Pipelined Data Flow Short Preamble Long Preamble Header Service Data 128 clocks 172 clocks 2 clocks 48 clocks 4 clocks 151 clocks 66 clocks

46. Controller Review

47. Conclusion • NOC based radio prototyping platform • Flexibility and scalability of FPGAs • Performance of ASICs • Paper submitted in conference IEEE INFOCOM, 2010 titled “Reconfigurable FFT Kernel for Network on Chip based Radio System Prototyping Platform ” 47

48. Questions