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ULTIMATE Design Review

ULTIMATE Design Review. Designers : G. Bertolone, C. Colledani, A. Dorokhov, W. Dulinski, G.Dozière, A. Himmi, Ch. Hu-Guo, F. Morel, H. Pham, I. Valin, J. Wang Test engineers : G. Claus, M. Gelin, M. Goffe, K. Jaaskelainen, M. Specht. Outline STAR Pixel Sensor Evolution MIMOSA-26 Design

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ULTIMATE Design Review

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  1. ULTIMATE Design Review Designers : G. Bertolone, C. Colledani, A. Dorokhov, W. Dulinski, G.Dozière, A. Himmi, Ch. Hu-Guo, F. Morel, H. Pham, I. Valin, J. Wang Test engineers : G. Claus, M. Gelin, M. Goffe, K. Jaaskelainen, M. Specht Outline • STAR Pixel Sensor Evolution • MIMOSA-26 Design • ULTIMATE Design & Optimisation • Pixel, Discriminator, Auxilliary Functional Blocks • Analog Characterization • Summary

  2. STAR PIXEL Detector • A 3 (+ 1) steps evolution: • 2007: A 3 plans telescope has been constructed Sensor:MimoSTAR-2, 5x5 mm2, analogue outputSubmitted Q2 2005 • 2012: A engineering prototype detector with limited coverage will be installedSensor:PHASE-1: 2x2 cm2, binary output, NO Zero suppression Submitted Q3 2008 + V2 in Q3 2009 • 2010: EUDET Telescope DeliverySensor:Mimosa26: 1x2 cm2, binary output, Zero suppression Submitted: Q4 2008 + HRes Q4 2009  Toward ULTIMATE • 2013: The pixel detector composed with 2 layers will be installed Sensor: ULTIMATE: 2x2 cm2, binary output, Zero suppression IPHC isabelle.valin@ires.in2p3.fr

  3. MIMOSA-26: Sensor for EUDET Beam Telescope Collaboration with IRFU/Saclay Main characteristics of MIMOSA26 sensor: • Column // architecture with in-pixel Amp & CDS and end-of-col. discrimination, followed by Ø • Active area: 21.2×10.6 mm² ,1152 x 576 pixels, pitch: 18.4 µm sp. < ~ 4 µm • Read out time < ~100 µs (104 frames/s)  suited for ~ 5 105 particles/cm²/s • Yield ~ 90% (75% fully functional sensors thinned to 120 µm + 15% (showing one bad row or column)) • Thinning yield to 50 µm ~ 90% IPHC isabelle.valin@ires.in2p3.fr

  4. Half reticle 1152 x 576 pixel matrix Integration time ~ 100 µs Pixel Pitch: 18.4 µm Temperature ~ 20 °C Light power consumption constrains: power consumption ~ 270 mW/cm2 Space resolution < ~ 4 µm No constrains on radiation tolerance Full reticle 960 x 928 pixel matrix Longer integration time ~ 200 µs Pixel pitch: 20.7 µm Temperature: 30 - 35 °C Power consumption: target ~ 100 mW/cm² Space resolution < 10 µm 150 kRad / yr & few 1012 Neq /cm² /yr 13780 µm 22710 µm 21560 µm 3280 µm 20240 µm ULTIMATE based on MIMOSA-26 sensor ULTIMATE MIMOSA26  Optimisation IPHC isabelle.valin@ires.in2p3.fr

  5. ULTIMATE Design and Optimization (1) • Reduction of power dissipation • Optimisation of pixel pitch v.s. non ionising radiation tolerance • Larger pitch: 18.4 µm  20.7 µm • Shorter integration time: 185.6 µs  Validated by the small prototype MIMOSA-22AHR • Optimisation of power consumption • Power supply voltage reduced from 3.3 to 3 V in ULTIMATE simulation • Design of pixel tested at 3V (in MIMOSA-22TER) with adjusted Vcl= 1.9 V: • 7% increased ENC, 15% decreased gain  Estimated simulation power consumption ~ 150 mW/cm² (at 3.3 V ) 135 mW/cm2 (at 3 V) • Pixel improvement: charge collection, radiation tolerance • High resistivity EPI substrate and radiation tolerance design  Validated by the small prototype MIMOSA-22AHR • Discriminator timing diagram optimization • Threshold non-uniformity reduction • On-chip voltage regulator design for pixel clamping voltage • Interferences minimisation on critical nodes • Zero suppression circuit (SuZe) adapted to STAR condition • Higher hit density  larger memories • Higher output frequency (80  160 MHz) • Enhanced testability MIMOSA-22AHR IPHC isabelle.valin@ires.in2p3.fr

  6. ULTIMATE Design and Optimization (2) • Pixel array: 928 rows x 960 columns • 20.7 µm square pixels • Pre-amplification and CDS inside each pixel • Column-level offset compensated discriminators • Zero-suppression circuit • Two output memories • Provided by the AMS foundry • Frequency distribution: • Input LVDS clock at 160 MHz • All column are readout in parallel at 5 MHz • 200 ns /row  (16 x 80 MHz) • Two LVDS sparsified data out at 160 MHz • On-chip programmable bias-DACs via a JTAG controller • Optional blocks (individuals test blocks) • Internal PLL at 10 MHz • On-chip voltage regulator for analogue power supply Functional block diagram IPHC isabelle.valin@ires.in2p3.fr

  7. CDS amplifier Output Buffer N_Well Diode ULTIMATE Optimization of Pixel (1) See Ref. A. Dorokhov et al., ULTIMATE Design Review Documentation, Part I, “Optimisation of Pixel Amplifier Design” Pixel Design • For binary readout, it is extremely important to have a correlated double sampling (CDS) and amplification inside pixel • Reduced discriminators threshold variation • Noise contribution from clamping voltage • Only NMOS transistors can be used in Pixel • Any additional NWELL used to fabricate PMOS transistor would compete with sensing diode for charge collection • One need to obtain higher amplifier gain • Maximized signal-to-noise ratio • For standard common source amplifier, special biasing with transistor M3 for the load transistor M2  increased AC gain by about ~ 2 • Adaptive feedback can be used to stabilize the operating point of the amplifier • Working conditions garanteed for every pixel in changing temperatue, irradiation… • Smaller variation of pedestals caused by the CMOS process parameters variation • 4 digital control signals per row: PWR_On, Slct_Row, Slct_Gr, Clamp • Slct_Row (16CK), PWR_On (2x16CK), Slct_Gr (16x16CK): power activate signals • Clamp: signal for CDS (3CK) • 1 column split into 58 groups of 16 pixels • Reduced SW capacitances • Current consumption: < ~ 60 µA/pixel IPHC isabelle.valin@ires.in2p3.fr

  8. ULTIMATE Optimization of Pixel (2) • Pixel Optimization • Different pixel amplifiers and sensing diodes were implemented in MIMOSA-22AHR • The pixel layout is optimized to have better radiation tolerance • The feedback transistor (M4) is replaced by its ELT variant Two stage amplifier Biasing via diode Two stage amplifier Biasing via transistor Common source amplifier Cascode amplifier Amplifiers implemented in MIMOSA-22AHR (clamping not shown) IPHC isabelle.valin@ires.in2p3.fr

  9. ULTIMATE Optimization of Pixel (3) MIMOSA-22AHR contains: Different classes of amplifiers: • Cascode • Common source • two stage (source follower AC coupled to cascode) • amplifiers with load in source (without feedback) Geometry variation: • Nwell diode • Pitch • Length of transistors' gate • ELT transistors Different substrates: - epi layer of 14 µm and low resistivity (< 20 Ω.cm) - epi layer of 10, 15 and 20 µm and high resistivity (< 400 Ω.cm) IPHC isabelle.valin@ires.in2p3.fr

  10. ULTIMATE Optimization of Pixel (4) Calibration peak for different chips, implemented in different substrate, measured at different clock frequencies, temperatures and irradiation • S7 (blue line, common source) has quite small gain variation for all measurements compared to green line (cascode) IPHC isabelle.valin@ires.in2p3.fr

  11. ULTIMATE Optimization of Pixel (5) Pixel schematic S7 has been chosen for ULTIMATE Optimized layout:  reduced parasitics and cross-talk MIMOSA-26 layout Beam test results Track reconstruction efficiency as function of fake hit rate, measured at 20C and 100 MHz Track reconstruction efficiency as function of fake hit rate, measured at 30C and 100 MHz IPHC isabelle.valin@ires.in2p3.fr

  12. Vclp_d RD VRef1 RD RD VRef2 Q CALIB LATCH A1 A2 A3 To Pixel RD RD LATCH CALIB RD Vclp_d Q ULTIMATE Optimization of Discriminator (1) See Ref. Y. Degerli et al, IEEE, Trans. Nucl. Sci. vol.52, No. 6, pp. 3186-3193, Dec. 2005 Discriminator design • Small input signal  Offset compensated amplifier stages • A/D conversion time = row readout time (200 ns) • Low current consumption ~ 70 µA/discri Column-level Double Sampling (DS)  reduce pixel to pixel dispersion (FPN) Pixel readout sequence • During the RD phase: • Sample the pixel signal (VRD) and its offset voltage • Sample the threshold voltage (VRef1) • Sample the offset voltage of the gain stages A2 and A3 (both input offset and output offset storage) • During the CALIB phase: • Sample the pixel voltage (VCALIB) and correct its offset • Sample the common-mode voltage of the threshold voltage (VRef2) • Amplify the signal (VRD-VCALIB) and the threshold voltage (VRef1-VRef2) and feed to the latch • During the LATCH phase: • Compare the pixel signal (VRD-VCALIB) to the threshold voltage (VRef1-VRef2), then give a logic level IPHC isabelle.valin@ires.in2p3.fr

  13. Pixel Array discriminator discriminator discriminator buffers 960 discriminators ~2 cm ULTIMATE Optimization of Discriminator (2) See Ref. I.Valin et al., ULTIMATE Design Review Documentation, Part II, “Optimisation of Discriminator Design” • Reference voltages (threshold) and clamping voltage are applied to 960 discriminators (~ 2 cm long) • Have to consider RC distribution line + successive charge rejections • Even an ideal source cannot provide stable references • Need stable voltages during “RD“ and “CALIB” periods (~ 30 ns) •  The discriminator row is divided into 4 groups • 4 bias DACs to compensate process dispersions of discriminators IPHC isabelle.valin@ires.in2p3.fr

  14. No. of discriminators ULTIMATE Optimization of Discriminator (3) • Discriminator timing diagram optimisation • Threshold non-uniformity reduction - Mimosa26 test results: Threshold dispersion of 1152 discriminators (divided in 4 groups) - It doesn't disturb chip operation if threshold is set to be higher than the dispersion Optimised timing diagram:(validated by a proto) Ideal timing diagram: Obtained timing diagram due to long track: Due to the delay, ex. charge injections by S3, S4 cannot be compensated by the auto 0 phase IPHC isabelle.valin@ires.in2p3.fr

  15. When RD signal is delayed compared to RD signal, the threshold dispersion can be reproduced in the small prototype In Ultimate sensor, the RD signal will be delayed compared to the RD signal to remove the systematic threshold dispersion ULTIMATE Optimization of Discriminator (4) • Optimized discriminator timing diagram • Validated in the small prototype MIMOSA-22AHR • 128 discriminators • Additional functionality • RD signal is delayed of 3 ns compared to RD signal • RD signal is delayed of 3 ns compared to RD signal • No delay Threshold dispersion as a function of the discriminator number for three different pixel rows IPHC isabelle.valin@ires.in2p3.fr

  16. ULTIMATE Auxilliary Functional Blocks (1) See ULTIMATE Design Review Documentation, Part III, “Auxilliary Functional blocks” • On-chip programmable bias-DACs via a JTAG controller • 8 bit current DAC • Range: 0 - 255 µA, Step= 1 µA • Good linearity • Current Reference • IRef = 1 µA • PSRRVDDA < - 50 dB, Power consumption ~ 300 µA • Temp. variation = 7.3 nA/°C • Reference voltages circuit for the discriminator • VRef2 DAC range: 0.5 V – 1.5 V, Step = 10 mV • VRef1 DAC range: -32 mV / +32 mV, Step = 250 µV • On-chip voltage regulator for pixel clamping • Adjustable output voltage by an internal 4 bit DAC • No external compensation scheme • LVDS Pads • LVDS transmitter • Can be set at high impedance by JTAG access • The current can be adjusted by DAC • LVDS receiver • Can be disable by JTAG access • The current can be adjusted by DAC Bias synthetic block diagram Most of these blocks have already been implemented and tested in many successive chips as PHASE1, MIMOSA-26… IPHC isabelle.valin@ires.in2p3.fr

  17. ULTIMATE Auxilliary Functional Blocks (2) Reference voltages circuit • The VRef1 voltage is built from the VRef2 voltage • Reduced process dispersions • Monte-Carlo simulation • Sigma of the threshold voltage (VRef1-VRef2) ~ 4 mV • Sigma of the threshold voltage after buffer ~ 7 mV • Near 100% of the chips could be adjustable by the DAC IPHC isabelle.valin@ires.in2p3.fr

  18. ULTIMATE Auxilliary Functional Blocks (3) • On-chip voltage regulators for pixel clamping have been implemented in MIMOSA22-AHR • Two different versions of circuits have been tested: INT and INT_LN • The contribution if noise from internal buffer has small value (<10%) and can be reduced using filter capacitance of few nF (estimated parasitic capacitance on the Vcl line) The voltage Vcl can be supplied externally (EXT) or generated in the chip ENC for different amplifier structures (S#) • Schematic of regulator INT_LN : • Low Dropout (Vin = 3 - 3.3 V) • Characteristics: Dropout voltage: ~ 0.3V, PSRR: ~ 40 dB, Noise: < 1 µV/sqrt(Hz) (at 10 KHz), Power consumption: <~ 1mW Absolute noise contribution from buffer as a function of pixel noise with external Vcl IPHC isabelle.valin@ires.in2p3.fr

  19. ULTIMATE Analog Characterization • Mode 1: Analog readout of entire matrix at low frequency (20 MHz) • The matrix is divided in stripes of 8 columns and fully scanned at each frame, then swapped with the next block of 8 columns at right and so on until all the columns are analyzed. • Mode 2: Analog readout of 8 pre-selected columns at nominal speed (80 MHz) • 8 pre-selected columns are chosen in the middle of the chip and connected directly to the 8 output pads. 8 output pads IPHC isabelle.valin@ires.in2p3.fr

  20. Summary • The design of ULTIMATE has been optimized: • Pixel design (schematic + layout): • cross-talk, parasitic capacitances, radiation tolerance • beam-test and lab test to choose the optimal version • Discriminator timing diagram: • Reduced threshold dispersion • Digital control circuit: • power consumption • speed • Design Status: • Simulation of all blocks performed and functionalities verified • Schematic and Layout: DRC and LVS passed • Mixed-Simulation to verify whole chip (Analogue + Digital Part) • Layout parasitic extraction to estimate possible degradation in worst case due to under estimated parasitic interconnects between blocks • In case of not sufficient performance, interconnect will be easily optimized to finalize the chip • Preliminary verification (DRC and Size for fabrication) made by CMP • Submission Plan: • The 9 th of December: Modifications following the common design review recommandations • Until the 17th of December: Verification at IPHC and at CMP • From 18th of December to 3nd of January: Laboratory is officially closed • Until the 14th of January: Verification • The 17th of January: Submission IPHC isabelle.valin@ires.in2p3.fr

  21. BACKUP IPHC isabelle.valin@ires.in2p3.fr

  22. Functional verification full chip Analog block Actual Status IPHC isabelle.valin@ires.in2p3.fr

  23. Power Dissipation Total current: 212 mA 152 mW/cm2 at 3.3 V 138 mW/cm2 at 3.0 V Chip area: 4.6 cm2 *4 transmitters, 1 receiver IPHC isabelle.valin@ires.in2p3.fr

  24. MIMOSA-22AHR IPHC isabelle.valin@ires.in2p3.fr

  25. Discriminator IPHC isabelle.valin@ires.in2p3.fr

  26. Discriminator Dynamic latch No static power consumption Good speed, switching time ~ 2ns Dedicated lines and pads for the supply and ground voltages Moderate gain ~ 4 Well defined output common-mode non linear gain IPHC isabelle.valin@ires.in2p3.fr

  27. Current Reference IPHC isabelle.valin@ires.in2p3.fr

  28. Reference Voltages Circuit IPHC isabelle.valin@ires.in2p3.fr

  29. LVDS Transmitter IPHC isabelle.valin@ires.in2p3.fr

  30. LVDS Transmitter Main characteristic in nominal condition T= 30°C, VDD = 3V, ilvds_tx= 40 µA, Cload = 10 pF) IPHC isabelle.valin@ires.in2p3.fr

  31. LVDS Receiver Nominal condition, T= 30°C, VDD=3V, tm, Vdiffpp = 200 mV, vcm = 1.2 V T= 125°C, VDD = 2.7 V, Vdiffpp = 200 mV IPHC isabelle.valin@ires.in2p3.fr

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