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1. Abstract

2. FPGA Implementation Of Non Linear Filters For Image Processing Mr. Hirschl Boaz Boaz.hirschl@intel.com Guide : Prof L. P. Yaroslavsky

3. Agenda • Background Non Linear Filters Hardware and Flow • Research Research goals Related work Algorithms • Conclusion Results Demo Bibliography

4. The big picture • Bio-Medical Imaging System require massive image processing • Image processing solution • Real time • Implemented in hardware • Focus on non linear filters. • FPGA

5. Non Linear Filters • Background Non Linear Filters Hardware and flow • Research Research goals Related work Algorithms • Conclusion Results Demo Bibliography

6. Non Linear Filters topics • Unified approach - definitions • What is a window • Example of Sliding window • Types of non linear filters • Neighborhood & Estimation • Non linear filters examples • Image enchantment • Histogram equalization • Other

7. Unification approach definition • Filters work in a moving window. • For each window a filter generate output value by means of a certain estimation operation ESTM applied to a certain set of values that we will call neighborhood NBH. L.P. Yaroslavsky, Nonlinear Signal Processing Filters: A Unification Approach.

8. What is a window example • We take an image • Look at a small part on the left upper corner • It is made of 7 x 5 pixels

9. Sliding Window • A 3 x 3 sliding window example • N = n x n Number Of elements • K nearest value (100,1) NBH example Sliding example

10. Unification approach pixel L.P. Yaroslavsky, Nonlinear Signal Processing Filters: A Unification Approach.

11. Unification approach nbh estm L.P. Yaroslavsky, Nonlinear Signal Processing Filters: A Unification Approach.

12. Window operations example • Lets look a 3 x 3 window • Vector it • Sort it • Min, Max, Median Rank

13. Median example • Example for 5x 5 window median filter. • The images are before and after running in the hardware simulator

14. Window operations example • Lets look a 3 x 3 window • Vector it • Get rank order statistics • Min, Max, Median • Create look up table • Histogram equalization Histogram

15. Unification approach – hist eq L.P. Yaroslavsky, Nonlinear Signal Processing Filters: A Unification Approach.

16. Unification approach – hist eq

17. Unification approach -example L.P. Yaroslavsky, Nonlinear Signal Processing Filters: A Unification Approach.

18. Hardware and flow • Background Non Linear Filters Hardware and flow • Research Research goals Related work Algorithms • Conclusion Results Demo Bibliography

19. Hardware implementations topics • FPGA • VHDL • Tools • Flow • Generation • Implementation • Verification • Analysis • VHDL Code generator • Verification suite

20. Gate Field Array FPGA - Architecture Programmable • CLB • IOB • OSCStartup • JTAG • Routes CLB IOB ROT LOG Configuration Memory Configure the FPGA to specific application Configure the FPGA to specific application Configure the FPGA to specific application

21. FPGA – Building blocks CLB • Look Up Table - LUT • FF • Routes

22. FPGA – Building blocks IOB • PAD • BUFFER • FF

23. FPGA – Building blocks ROUTE • PSM - Programmable Switching Matrix

24. VHDL • Hardware Description Language • Standard IEEE language for hardware generation & simulation • Top-Down design • Design reuse • Behavioral description • RTL Register Transfer Logic example

25. FLOW – General • Entering the design • Synthesizing • Func Simulation • Implementation • Time Simulation • Programming file

26. TOOLS • Matlab - modeling of a filter in HW writing style. • Xilinx WebPACK synthesizer, mapper , place and route • Model sim – VHDL model simulation • VHDL code generator

27. VHDL code generator • One of the novelties in our work • Creates the required VHDL code • Support all window sizes • Vendor independent • Simple to use.

28. FPGA Design – verification • Take an image • MATLAB Make it into a stream files • Send it to simulator • Receive the simulator output vector stream • Verified in MATLAB environment VHDL model result Vs Matlab model result.

29. Research goals • Background Non Linear Filters Hardware and flow • Research Research goals Related work Algorithms • Conclusion Results Demo Bibliography

30. Research goals topics • Algorithms implementation study • Create building blocks for real time image processing – LEGO style • Graphic Co-Processor • Long term goals

31. Algorithms implementation study • Compare different implementations for the same algorithms • Compare variations of the same algorithms • Area • Speed - Performance • Latency • Power • Other studies : • Silicon regularity • Primitives usage • Pipe lining and routing issues

32. Create Processing Blocks • Serial / Parallel sorter • Serial / Parallel Rank computer • Serial / Parallel Occurrences computer • Serial Histogrammer • Histogram equalization • Focus on the engine • Intellectual Property (IP) philosophy

33. Create Processing Blocks • A sorter – in this example 3 input vector

34. Create Processing Blocks • A median filter to denoise image Noisy Image Denoise Image

35. Graphic Co-Processor • Advanced Bio medical imaging systems • Accelerate graphic performance • Concentrate on non linear filters • Dedicated hardware • Single Instruction Multiple Data – SIMD • Configurable processor.

36. Artificial retina • Numerous works trying to progress in the field.

37. Related work • Background Non Linear Filters Hardware and flow • Research Research goals Related work Algorithms • Conclusion Results Demo Bibliography

38. Related work topics • Graphic processing hardware language • Specific image processors • Application Specific Integrated Circuit • ASIC’s and boards • Sorters • Histogrammer

39. Image language- crooks • In this works the group developed a high level language that is based on a set of image processing commands. • This language can be synthesize a flexible HW solution • Based on specific HW – non generic • Limited abilities P. Donachy, Design and Implementation of a High Level Image Processing Machine Using reconfigurable Hardware. PhD thesis, The Queen’s university of Belfast , Ireland 1996.D. Crookes, K. Benkrid, J. Smith, A. Benkrid, High Level Programming for Real Time FPGA-Based Video Processing, Proceedings of ICASSP2000, Istanbul 2000.D. Crookes, K. Benkrid, A. Bourdane, K. Alotaibi, A. Benkrid, Design and implementation of high level programming environment for FPGA-based image processing, IEEE Proc visual image process, Vol. 147 No. 4 August 2000.

40. ASIC Image processor • A full fixed image processor • Implemented in ASIC • Required large memory • Parallel approach • Off line processing • 100 MHz = 0.1Ghz = 10 ns S. Muller, A New Programmable VLSI Architecture for Histogram and Statistics Computation In Different Windows,IEEE08186-7310-9/95 Hamburg Germany 1995.

41. Fixed Image processor • A image processor that is able to do • For a 3x3 window • Median, Morphological , addition , subtraction , mostly linear • 100 MHz = 0.1Ghz = 10 ns K.wiatr, Pipeline Architecture of specialized reconfigurable processor in FPGA structures for real time pre-processing,IEEE1089-6503/98 University of Krakow , Poland 1998.

42. Other • Other sorters used specific cells • Combination of HW and software solution R. Lin, S.Olariu, “Efficient VLSI Architecture for column sort”. IEEE Transactions on VLSI system Vol 7, NO 1, March 1999.M. Bednara, O. Beyer, J. Teich, R. Wanka, “Tradeoff Analysis And Architecture Design Of Hybrid Hardware/Software Sorter”, Application-Specific Systems, Architectures, and Processors, 2000. Proceedings., 10-12 July 2000 pg 299 –308.

43. Algorithms • Background Non Linear Filters Hardware and flow • Research Research goals Related work Algorithms • Conclusion Results Demo Bibliography

44. Algorithms topics • Sorters • Serial / Parallel • Rank computer • Serial / Parallel • Histogrammer • Serial / Parallel • Histogram equalization

45. Sorter Serial - basic • Cell • Value • Age • Sorter • Cells main shadow • Full Sorter • Not a First In First Out FIFO

46. Sorter Serial – cells • Main Cell • Shadow cell A 3 bit sorter

47. Parallel Sorter - basic • Distributed Arithmetic's Example

48. Parallel Sorter - pipeline • Fully pipe lined sorter. • Partly pipe lined sorter • Interesting enough the partly pipe line sorter is faster in some cases. • For example Adjustable parallel sorter works at 15 % faster then fully pipe lines sorter at 150 MHz.

49. Parallel Rank computer • .Compare each pair • Sums up the comparisons • Use of comparator primitives SRC OCC HIST Based on Prof Yaroslavsky work

50. Serial Rank computer - basic • .Cell • Value • Rank • Computer