Project Overview

1. 913.001 Layout Techniques for Cost-Driven Control of Lithography-Induced VariabilityDennis Sylvester / Andrew B. KahngU. Michigan EECS Dept. / UC San Diego ECE Dept.

2. Project Overview Objective: Develop cost models, design rules, layout methods, and tools to: (1) minimize costs associated with resolution enhancement techniques (RETs), and (2) limit lithography-induced variability • Faculty • Dennis Sylvester, University of Michigan EECS Dept. • Andrew B. Kahng, University of California, San Diego ECE Dept. • Students • Jie Yang, PhD expected 2006 • Puneet Gupta, PhD expected 2006 • Mentors • Luigi Capodieci, AMD • Lars Liebmann, IBM • Karl Perrey, Intel • (Warren Grobman, Motorola)

3. RETs for Subwavelength Lithography • WYSIWYG (layout = mask = wafer) failed starting with 350nm generation • Optical lithography: feature size limited by diffraction • Available knobs • aperture: OPC • phase: PSM •  RETs

4. Optical Proximity Correction (OPC)

5. conventional mask phase shifting mask glass Chrome Phase shifter 0 E at mask 0 0 E at wafer 0 0 I at wafer 0 Phase Shifting Mask (PSM)

6. Mask Component of Manufacturing NRE Half of all mask sets used for < 570 wafers (< 100K parts) OPC, PSM, Fill  increased feature complexity Vector scan: Write cost proportional to feature complexity Difficult to inspect, verify masks! M. Rieger, Avant! – ISMT Mask-EDA Workshop July 2001

7. Context-Dependent Fracturing Same pattern, different fracture P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001

8. ITRS Maximum Single Layer File Size MEBES Data Volume (GB) Year P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001

9. ALTA-3500 Mask Write Time Write Time (Reformat + Print) (Hrs) ABF Data Volume (MB) P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001

10. RET Issues • PSM and lithography equipment choices (e.g., OAI) constrain layout, explode mask costs • Forbidden configurations (wrong-way critical-width doglegs, or diagonal features) • Cost-reducing variants (IDEAL, GRATEFUL) more constraining • Process window and yield enhancement: ditto • Forbidden width-spacing combinations (defocus window sensitivities) • Complex “local DRCs” • OPC subresolution assist features: ditto • Notch rules, critical-feature rules on local metal • Other • Dummy fill changes RCX results, creates inter-layer dependencies, increases data volume • halation rules (width- and length-dependent spacing)

11. Example: Off-Axis Illumination • Different variants of off-axis illumination act to: • Amplify dense lines while attentuating larger pitches • Print only axis-parallel lines, not 45º lines F. Schellenberg, Mentor

12. RET-Related Needs in 2001 ITRS • Function- and cost-aware OPC, PSM, dummy fill • Real goal = predictable circuit performance and function • Tools must understand functional intent • Make only corrections that gain $$$, reduce performance variation • Make only corrections that can be manufactured and verified • Fail only mask errors that affect function • Understand (data volume, verification) costs of breaking hierarchy • Fix broken flows • Making same OPC corrections 3x (library, router, PV tool) • Layout signoff w/o comprehending later RET insertion (e.g., fill)

13. Key Question Which should be developed: (A) circuit design techniques that can deal with variability, or (B) process techniques that reduce variability? • At < 65nm, variation-tolerant circuit techniques may be a more cost-effective way to combat rising process uncertainties • Should seek better bang for the buck in applying RETs • Function-, cost-driven corrections • Synergies among various correction techniques (e.g., fill helps OPC)

14. Quantifying Impact of RETs • Performance fluctuations due to dummy fill • Varying filling constraints, physical CMP models, tiling rules • Gate delay impact unclear • Grounded fill  inductive impact? • MOSFET I-V characteristics (including Ioff) with and without OPC/PSM • Varying proximity, layout configuration, gate dimensions • Layout density and performance • PSM-compliant libraries trade density for “free composability” • Bent gates no longer available • Intermediate-pitch wiring may underperform due to variability increase stemming from lack of subresolution assist features

15. Investigating the Variability/Cost Relationship Initial driving question: How does the maximum value design compare to the maximum performance design? • Maximum value is driven by parametric distributions as well as value distributions (e.g., bin sorting) • What are the design implications for a value maximized design? • E.g., rely more heavily on spatial correlations or strive for more random behavior (averaging effects) ??? • To measure $/wafer, we need (1) detailed models of process variability, and (2) models of how chip parameters (frequency, testability, etc.) affect value

16. Investigating the Variability/Cost Relationship (1) • (A) Build a taxonomy of variability sources • Intrinsic vs. dynamic (Vdd,temp) • Random vs. systematic • Intra-die, Intra-reticle, Intra-wafer, etc. • Including correlations (local, global) • (B) Incorporate a smart Monte Carlo approach • Based on performance sensitivity to sources of uncertainty • (C) Build generic critical path models • Delay-constrained vs. power-constrained • + Ring-oscillator, clock tree, etc. models

17. “Mapping Design to Value”: (1) Across-Wafer Frequency Variation

18. “Mapping Design to Value”: (1) Across-Wafer Frequency Variation

19. “Mapping Design to Value”: (2) Can we combine (1) and (2) to drive design optimizations?

20. “Mapping Design to Value”: (2) Can we combine (1) and (2) to drive design optimizations?

21. Research Timeline • Year 1: Assess cost vs. variability tradeoffs, develop cost models for RETs • Year 2: Develop layout methods and tools for cost-driven insertion of RETs while meeting performance goals • Year 3: Model calibration/verification using test structures, circuit layout approaches to account for RET-based constraints

22. SPARE SLIDES

23. RET Resource Requirements Grobman, Motorola

24. RET Roadmap 0.25 um 0.18 um 0.13 um 0.10 um 0.07 um Rule-based OPC Model-based OPC Scattering Bars AA-PSM Weak PSM Rule-based Tiling Optimization-driven MB Tiling Litho CMP Number Of Affected Layers Increases / Generation 248 nm 248/193 nm 193 nm W. Grobman, Motorola – DAC-2001

25. Mask Data and the $1M Mask NRE • Too many data formats • Most tools have unique data format • Raster to variable shaped-beam conversion is inefficient • Real-time manufacturing tool switch, multiple qualified tools  duplicate fractures to avoid delays if tool switch required • Data volume • OPC increases figure count acceleration • MEBES format is flat • ALTA machines (mask writers) slow down with > 1GB data • Data volume strains distributed manufacturing resources • Refracturing mask data • Before: mask industry never touched mask data (risky, no good reason) • Today: 90% of mask data files manipulated or refractured: process bias sizing (iso-dense, loading effects, linearity, …), mask write optimization, multiple tool formats, …

26. Process Variation Sources • Design  (manufacturing variability)  Value • Intrinsic variations • Systematic: due to predictable sources, can be compensated during design stage • Random: inherently unpredictable fluctuations and cannot be compensated • Dynamic variations • Stem from circuit operation, including supply voltage and temperature fluctuations • Depend on circuit activity and hard to be compensated • Correlations • Tox and Vth0 are correlated due to • Line width and spacing are anti-correlated by one; ILD and interconnect thickness also anti-correlated

27. Lens Towards Lens Wafer Plane Edge: High Aberrations Center: Minimal Aberrations Many Variability Sources… • Example: Field-dependent aberrations cause placement errors and distortions R. Pack, Cadence