Logic Analyzers Neophyte Training March 2013

1. Logic Analyzers Neophyte Training March 2013 Chee-Lam, Chan 陈志霖DDS Business Development Manager

2. Introduction The goal of this session is to help you learn about… • Where to sell…Who buys logic analyzers • What a logic analyzer is and why customers need one • When to use a logic analyzer versus an oscilloscope • Why buy Agilent? Competitive Information • Available sales tools and resources

3. Longhaul MAN WAN Technology Deployment Eco-System Infrastructure Interfaces Desktop Chipset Enterprise Infrastructure DDR CPU o SATA II DVI DP HDMI HDD HT QPI DDR, BoB CEI GbE FC NB FibreChannel Storage SAN PCIe PCIe FC GbEthernet CEI GbE GbE HT PCIe Server DMI HD Audio LAN Ethernet Ethernet SB SATA Infiniband USB SFP Module SFI GbE PCI DWDM LTE PON PON RH OLT RFIC WiMAX PON PON OBSAI-RP3(01) DP HDMI USB digRF CPRI BSC/ RNC XFP Module XFI OBSAI-RP1/2 BTS Tx/Rx BBIC DDR USB OBSAI-RP3(01) AP A/V Decoder/ Processor DSI CSI SONET CPRI Telco Switch MIPI D-Phy RH DSI BBIC RFIC OTN WiHD Public Wireless Infrastructure Mobile Device Public Wireline Infrastructure Consumer

4. Digital – it’s everywhere, and so is DDS! Computers/ Server Mobile Computing Computer Chipset DDR CPU o DVI DP HDMI HT QPI DDR, BoB NB PCIe PCIe HT PCIe DMI HD Audio SB SATA USB Entertainment Systems Communication PCI RFIC digRF BBIC DDR USB AP DSI CSI MIPI D-Phy DSI

5. Digital Debug Solution (DDS) Markets Computer/Storage Devices Consumer Mobile Computing MIPI MPHYCSI3/DSI2 MIPI MPHYLLI MIPI DPHY CSI-2/DSI UFS/UniPro DigRF v3 /v4 USB3.0 USB2.0/3.0 DDR3 LPDDR/DDR2 HDMI 1.4b MHL SATA/SAS 1, 2, 3 PCIe1/2 PCIe 3 DisplayPort1.2 Product Debug Timing Analysis ARM Debug ADC analysis FPGA/ASIC Digital IQ Analysis General Purpose and Embedded

6. Who Are Logic Analyzer Customers? • Anyone with digital content in their design(Virtually all designs have digital content) • Anyone with FPGAs or memory in their design (Virtually every design has an FPGA and memory.) • Logic analyzer customers are in all industry segments • Aero/Def • Consumer • Communications • Computer • Semiconductor • Wireline, Wireless • Education

7. How to Determine What’s Right for the Application: Oscilloscope or Logic Analyzer?

8. When to Use an Oscilloscope • Parametric measurements • 2 to 4 signals • Precise time vs voltage relationships Rise Droop Overshoot Valid Logic 1 Ringing Pulse Width Valid Logic 0 Rise Time Fall Time

9. 1 0 2 1 2 3 When to Use a Logic Analyzer • Cause and effect timing relationships between inputs and outputs • Many channels simultaneously • Multiple bus correlation measurements X1 INPUTS X2 X/Y Y0 INPUTS Y1 OUTPUTS OUTPUTS Y2 Y3

10. When Do I Position a Logic Analyzer vs MSO?

11. Using a Logic Analyzer vs an Oscilloscope

12. Digital Channel Comparison

13. A Logic Analyzer is a Tool That Gives you insight into the operation of a digital circuit by • Connecting to the DUT (Device Under Test) • Capturing and storing digital data Analyzing the stored data and displaying the results

14. A Logic Analyzer is a Tool That Gives you insight into the operation of a digital circuit by • Connecting to the DUT (Device Under Test) • Capturing and storing digital data Analyzing the stored data and displaying the results

15. Probing Performance, Accuracy, and Connectivity Flying Lead Probes Connect to individual, widely dispersed signals at IC pins, traces, pads and vias Connector Probes Industry standard connections to many signals in one easy connection Soft Touch Connectorless Probes Minimize loading, reduce cost & connect even on contaminated surfaces Device Specific Probes Extensive range of processor and bus probes FPGA Dynamic Probe Move internal probe points in seconds without design changes DDR2 & DDR3 BGA Probes Eliminate the need for upfront planning or redesign

16. A Logic Analyzer is a Tool That Gives you insight into the operation of a digital circuit by • Connecting to the DUT (Device Under Test) • Capturing and storing digital data Analyzing the stored data and displaying the results

17. Understanding How a Logic Analyzer Works Timing Mode? State Mode? Trigger?

18. Timing Mode: How It Works V Threshold Output (0 or 1) V Input + Latch V Output Comparator Internal Analyzer Clock Simply put – a logic analyzer captures 1’s and 0’s (highs and lows).

19. State Mode: How it Works Data is only clocked in on the edge of a signal from the DUT DATA AA 0C 61 B3 CLOCK Data Clock 1 AA 2 0C 3 B3

20. What is a Trigger? Linear Model Beginning 3 Trigger 16 17 Pre-Store 18 15 14 19 20 13 21 12 Ring Model 11 22 • Trigger 18 10 3 4 9 Post-store 8 5 • Post-store 6 7 End 22 A Trigger is an event that, when detected, allows the logic analyzer to fill its trace memory and complete the measurement.

21. The important of memory depth Display Tool Trace Memory Trigger Captured Activity System Activity

22. Defining Simple Trigger Events Trigger on Bus values Trigger on Signal values

23. Defining Advanced Trigger Events

24. A Logic Analyzer is a Tool That Gives you insight into the operation of a digital circuit by • Connecting to the DUT (Device Under Test) • Capturing and storing digital data Analyzing the stored data and displaying the results

25. Standard Viewing Displays ListingProcessor Pneumonics, Souce code Waveform Accumulate, Overlay, Import Scope Traces

26. Main Uses of a Logic Analyzer Clear eye opening suggests good SI Adjust threshold and sampling position for accurate data capture Find signal glitches Bad bit (inactive data line) • Digital debug (signal interaction) • Stuck bits (easy to find with activity indicators) • Precise timing between events, show wrong timing relationships between signals • Find signal glitches • Multichannel signal integrity

27. Main Uses of a Logic Analyzer Cross Bus Correlation Inverse assembler / Decoder DDR Protocol Compliance Test Viewscope • Functional validation (system level test  cross bus correlation) • Verify events happen in the correct sequence, verify whether or not particular events happen • Ensure the correct data is on the bus • Correlate activity across buses and subcomponents, analyze complex buses and protocols • Perform compliance tests at the protocol level • Inverse assemble a microprocessor’s signal outputs and show what code was running • Find the cause of elusive system crashes • Viewscope functionality

28. Main Uses of a Logic Analyzer Is my bus efficient? Read/Write efficiency check • Characterization • Determine how much margin you have in your design • Performance optimization • Identify opportunities to improve system performance

29. Agilent U4154A World’s Fastest Logic Analyzer • Highest confidence in measurement accuracy • Fastest State Speed, 4Gbps on Half Channels and 2.5Gbps on Full Channels • Fastest Timing Speed, 2.5Gbps on Full Channels • Fastest Trigger Sequence Rate, 2.5GHz • Data valid window ≤100mV x 100ps • Sampling Resolution, 5ps by 2mv Key Applications DDR 2/3/4 FPGA Debug ViewScope ADC Analysis Digital VSA

30. AXIe-based Modular Platform For Multiple Buses U4154A Logic Analyzer M9502A 2-slots AXIe chassis U4301A PCIE Gen 3 Analyzer U4421A MIPI D-PHY M9505A 5-slots AXIe chassis U4431A MIPI M-PHY U4998A HDMI/MHL Analyzer

31. 16800 Series Portable Logic Analyzers Affordable fixed configurations Up to 450 MHz state and 4 GHz timing Up to 32 M memory depth 8 models support a wide range of applications: 34, 68, 102, 136, or 204 channels Built in 48-ch pattern generator available on select models Portable and Modular Logic Analyzer 16900 Series Modular Logic Analyzers • Flexibility to configure the system for specific acquisition and stimulus needs (2 or 6 slot models) • Long-term investment protection – upgrade or re-configure as needs evolve • Maximize measurement capability: • Highest channel counts (up to 612 per frame) • Highest state (2.5 GHz) & timing (8 GHz) • Deepest memory depth (up to 256 M) • Single ended & differential signal supported

32. Agilent Logic Analyzer Portfolio Ultra High End New U4154A -01G Entry level State Mode option High End Price U4154A -02G 4Gb/s State 68 ch 2.5Gb/s State 136 ch 12.5GHz TZ U4154A -01G 2.8Gb/s State 68 ch 1.4Gb/s State 136 ch 12.5GHz TZ Mid Range Entry Class 16962A 2.5Gb/s State 34 ch 2Gb/s State 68 ch 16950B 800 MHz State 34 ch 667 MHz State 68 ch 16910/11A 500Mb/s State 16800 series 500Mb/s State Colorized eye scans (Price range includes frame, modules, memory depths & state speeds)

33. U4154A -01G and U4154A -02G Differentiators

34. 02G Competitive Comparison Agilent Confidential Agilent Confidential

35. 01G Competitive Comparison Agilent Confidential Agilent Confidential

36. Agilent 16800 vsTek TLA6400 Agilent Confidential Agilent Confidential

37. Agilent 16800 vsTekTLA6400 (Con’t) • New TLA6400 Series Overview • Tek discontinued TLA5000B and TLA6200 Series LAs, new TLA6400 Series introduced on 21st Aug. • The TLA6400 is a repackaging of detuned TLA7BB logic analyzer module(s) and TLA7012 frame into a single monolithic instrument. • There is no new measurement technology or software features associated with this introduction. • This is similar to Tek’s TLA6200 series logic analyzer announcement (September 2010) which has not been successful to date. • The frame CPU and operating system have been upgraded (Windows 7 64-bit operating system). • Feature wise this product competes with Agilent’s 16950B modular logic analyzer. Agilent Confidential Agilent Confidential • Lead with Agilent’s 16800 LA differentiators to avoid deep discounts: • ONLY 204-channel portable logic analyzer. • ONLY portable logic analyzer with built-in 48-channel pattern generation. • ONLY portable logic analyzer with 2 independent analyzers (available on six models >34 channels). • Digital VSA – Lock-out application. Perform time, frequency & modulation domain analysis on digital baseband & IF signals. • FPGA Dynamic Probe – Best in class FPGA debug with automated bit map-ping. • Eye Scan – simultaneous eye diagrams across all signals (best used at clock rates >200 MHz). • Viewscope– No need for expensive cable to integrate time-correlated scope traces into logic analyzer waveform display.

38. Agilent 16800 vsTekTLA6400 (Con’t) Agilent Confidential Agilent Confidential

39. Considerations When Configuring a Logic Analyzer • The key questions to ask when configuring a logic analyzer • What kind of application?  Distinguish either Logic Analyzer or Protocol Analyzer • How do you intend to probe your signals?  Probing options • What are the signal speeds you want to capture?  State/Timing speeds • What is your maximum number of signal/channel?  Number of channels • How much data do you need to see?  Memory depth

40. Your Local Buddies Division Local Support Contacts • US - David Bottorff, BOTTORFF,DAVID (A-ColSprings,ex1) • Japan - KatsuyoshiHoribe, HORIBE,KATSUYOSHI (A-Japan,ex1) • SAP - VimalRanganathan, RANGANATHAN,VIMALKUMAR (A-USA,ex1) • GCR + Korea - Chee Lam Chan, CHAN,CHEE-LAM (A-Malaysia,ex1) • EMEA - YoramShimoni, SHIMONI,YORAM (A-Israel,ex1) Technical Support • iCare - http://disceval.cos.agilent.com/icare/

41. Available Logic Analyzer Sales Tools & Resources Field Portal • http://fieldcom.cos.agilent.com/portal.php • Asia Monthly Digital Newsletter • Make sure you got a copy, else contact Chee-Lam, Chan.

42. Useful Products URL

43. Demo Center, your BEST offline demo tool • Demo Center • Install the logic analyzer software on your PC. Demo the logic analyzer interface with previously captured traces (included with Demo Center)

44. Questions

45. Backup Application: FPGA FPGA/ASIC

46. FPGA Functional Debug With Logic Channels Agilent MSO/LA FPGA Pins Probe points • 1 signal per FPGA pin; usually pin limited • Requires design change to view new signals (iterative debug) • Change in HDL code • Manual management of physical and logical signal mapping to MSO digital channels and labels / Auto pins mapping in Logic Analyzer • Equal time investment for each iteration

47. FPGA Dynamic Probe Application Incremental Real Time Internal Measurements Without: • Stopping FPGA • Changing the design • Modifying design timing Quick Setup • Mapping of FPGA pins to MSO digital channels or LA • Signal and bus names

48. USB or Parallel Control access to new signals via JTAG JTAG FPGA Dynamic Probe Application FPGA Dynamic Probe SW application supported with all current Agilent MSOs Probe core output PC Board FPGA Insert ATC2 core with Xilinx Core Inserter ATC2

49. XilinxExample: Agilent Trace Core (ATC2) ATC2 Output to FPGA pins for debug • Up to 64 signal banks • All banks have identical width (4 to 128 signals wide) 4 - 128 4 - 128 4 - 128 Up to 16 digital channels on MSOs Selection MUX 4 -128 4 -128 clk clk From 34 up to 9,792 channels on LA JTAG Select Change signal bank selection from MSO`

50. FPGA debugging tool Agilent Confidential Agilent Confidential Yes, we will support the FPGA latest model, Virtex 6 and Spartan 6. LPT will keep flowing the FPGA market trend. Still remember our strength in FPGA debugging?