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Software/Hardware Prototyping

Software/Hardware Prototyping. Cyrus Trainor, Ankur Agarwal, Ravi Shankar. Computer Science and Engineering, FAU. OPP System Design Flow. OPP Relevance. Requirements/ Specifications. System Modeling & Analysis. Subystems’ Integration. Virtual Prototype. Impulse Platform

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Software/Hardware Prototyping

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  1. Software/Hardware Prototyping Cyrus Trainor, Ankur Agarwal, Ravi Shankar Computer Science and Engineering, FAU

  2. OPP System Design Flow OPP Relevance Requirements/ Specifications System Modeling & Analysis Subystems’ Integration Virtual Prototype

  3. Impulse Platform Libraries C languageapplications GenerateFPGAhardware Generatehardware interfaces Generatesoftwareinterfaces HDL files HDL files Software libraries CoDeveloper with Impulse C • Myth: • A HW PROTOTYPING ENVIRONMENT • Create, Partition, Accelerate, Debug using StandardC • Use Impulse C functionsto partition the applicationinto hardware and softwareprocesses. • Use CoDeveloper to compilehardware processes to HDLand generate hardware streamand memory interfaces. • Export hardware and softwareblocks to selected synthesis,simulation and FPGA platformgeneration tools.

  4. H/Wprocess H/Wprocess S/Wprocess H/Wprocess H/Wprocess From C Application to FPGA Platform H/Wprocess S/Wprocess S/Wprocess S/Wprocess H/Wprocess • Platform librariessupport existingFPGA hardwaresynthesis andsoftware compilerenvironments • Automatic generationof hardware/softwareinterfaces is optimizedfor target platforms • FPGA hardwareis automatically createdfrom C languageprocesses The result?Accelerated softwarewith minimal need for hardware or FPGA design knowledge! S/Wprocess

  5. Develop and debug the application usingstandard C tools such as Visual Studioor gcc/gdb. Use the Impulse C tools to generatesynthesizable hardware and APUinterfaces for specific C-languagesubroutines. Combine the generated hardware andsoftware IP with other components inXilinx Platform Studio or AlteraSOPC Builder. Generate a bitmapand download to the target board.

  6. PlatformspecificIP blocks Impulse CIP blocks Embeddedsoftwareapplications C applications Embedded OS Libraries Externalmemory Embeddedprocessor Processor peripherals On-chipMemory IP Blocks Platform-specific interfaces(e.g. bus structures) FPGA Platform Tools(e.g. Xilinx EDK or Altera SOPC Builder) Cross-compiler,linker, etc. FPGA Platform Integration with FPGA Platform Tools

  7. What is Impulse C? • A library of functions compatible with standard C • Functions for describing parallel processes • Functions for application partitioning • Functions for desktop simulation and instrumentation • A software-to-hardware compiler • Generates optimized HDL, ready for FPGA synthesis • Generates FPGA software-to-hardware interfaces • Purpose • Describe hardware accelerators using standard C • Move computationally-intensive functions to FPGAs • Use one language for both software and hardware

  8. Shared memory block reads/writes C language process Stream inputs Stream outputs Signal inputs Signal outputs Register inputs Register outputs Software processes set up data and perform non time-critical functions App Monitor outputs Hardwareprocesses are independently synchronized and perform most of the work An Impulse C Process Multiple methods ofprocess-to-processcommunicationsare supported

  9. H/W process S/W process S/W process H/W process H/W process Parallel Programming Model • Communicating Process Programming Model • Buffered communication channels (FIFOs) to implement streams • Supports dataflow and message-based communications between functional units and local or shared memories • Supports parallelism at the application level and at the level of individual processes (via automated scheduling/pipelining)

  10. Digital camera CCD CCD preprocessor Pixel coprocessor D2A A2D lens JPEG codec Microcontroller Multiplier/Accum DMA controller Display ctrl Memory controller ISA bus interface UART LCD ctrl Digital Camera Example

  11. Components of Digital Camera • CCD Capture - Modeled as SW Process • Image Correction - Modeled as SW Process • Red Eye Reduction - Modeled as HW Process • Image Compression - Modeled as HW Process • Image Output - Modeled as SW Process • Components will be modeled in HW/SW • Computation extensive blocks will be modeled in HW • Iterative Process

  12. Application Monitor Generate block diagrams Output messages Observe data streams Identify bottlenecks Visualize buffers Identify deadlocks Improve synchronization

  13. Hardware Design Analysis Visual representation paired with source code Estimated path delays Shows loop latencies Maximum unit delay Effective pipeline rates Pipeline graphs

  14. Design flexibility One language Reconfigurable solutions Algorithm Acceleration Software/Hardware Prototyping Parallel Computing Optimized HDL Export to FPGA Performance Extraction Conclusion

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