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Tomasulo Organization

Tomasulo Organization. FP Registers. From Mem. FP Ops Queue. Load Buffers. Load1 Load2 Load3 Load4 Load5 Load6. Store Buffers. Add1 Add2 Add3. Mult1 Mult2. Reservation Stations. To Mem. FP adders. FP multipliers. Common Data Bus (CDB). Three Stages of Tomasulo Algorithm.

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Tomasulo Organization

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  1. Tomasulo Organization FP Registers From Mem FP Ops Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3 Mult1 Mult2 Reservation Stations To Mem FP adders FP multipliers Common Data Bus (CDB) (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  2. Three Stages of Tomasulo Algorithm 1.Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2.Execute—operate on operands (EX) When both operands ready, start to execute; if not ready, watch Common Data Bus for result 3.Writeresult—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available • Normal data bus: data + destination (“go to” bus) • Common data bus: data + source (“come from” bus) • 64 bits of data + 4 bits of Functional Unit source address • Write if matches expected Functional Unit (produces result) • Does the broadcast • Completion latencies for instructions in following example slides: clocks after start EX, +1 for LD; 2 for Fl .pt. +,-; 10 for *; 40 for /. (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  3. Reservation Station Components Op: Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of source operands for Op • Each store buffer has a V field, for the result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) • Note: Qj,Qk=0 => ready • Store buffers have only one Qi for RS producing result Busy: Indicates reservation station or FU is busy Time: After FU starts EX, number of cycles yet to do Register resultstatus—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register. (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  4. Cycle instruction EXecution starts Instruction stream 3 Load/Buffers FU count down 3 FP Adder R.S. 2 FP Mult R.S. Clock cycle counter Tomasulo Example EX (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  5. Tomasulo Example Cycle 1 EX (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  6. Tomasulo Example Cycle 2 EX 2 Note: Can have multiple loads outstanding (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  7. Tomasulo Example Cycle 3 EX 2 3 • Note: register names are removed (“renamed”) in Reservation Stations; MULTD issued; (clocks: +1 for LD; 2 FP +,-; 10 for *; 40 for /) • Load1 completing; what is waiting for Load1? (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  8. Tomasulo Example Cycle 4 EX 2 3 • Load2 completing; what is waiting for Load2? Mult1, Add1 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  9. Tomasulo Example Cycle 5 EX 2 3 5 5 • Timer starts down for Add1, Mult1 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  10. Tomasulo Example Cycle 6 EX 2 3 5 5 • Issue ADDD despite name output-dependency on F6? (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  11. Tomasulo Example Cycle 7 EX 2 3 5 5 • Add1 (SUBD) completing; what is waiting for it? (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  12. Tomasulo Example Cycle 8 EX 2 3 5 5 8 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  13. Tomasulo Example Cycle 9 EX 2 3 5 5 8 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  14. Tomasulo Example Cycle 10 EX 2 3 5 5 8 • Add2 (ADDD) completing; what is waiting for it? F6 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  15. Tomasulo Example Cycle 11 EX 2 3 5 5 8 • Write result of ADDD here? • All quick instructions complete in this cycle! (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  16. Tomasulo Example Cycle 12 EX 2 3 5 5 8 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  17. Tomasulo Example Cycle 13 EX 2 3 5 5 8 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  18. Tomasulo Example Cycle 14 EX 2 3 5 5 8 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  19. Tomasulo Example Cycle 15 EX 2 3 5 5 8 • Mult1 (MULTD) completing; what is waiting for it? Mult2, F0 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  20. Tomasulo Example Cycle 16 EX 2 3 5 5 16 8 • Must wait for Mult2 (DIVD) to complete • (skip 38 no-new-action cycles … ) (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  21. … Tomasulo Example Cycle 55 EX 2 3 5 5 16 8 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  22. Tomasulo Example Cycle 56 EX 2 3 5 5 16 8 • Mult2 (DIVD) is completing; what is waiting for it? F10 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  23. Tomasulo Example Cycle 57 EX 2 3 5 5 16 8 • Once again: In-order issue, out-of-order start of execution, and out-of-order completion. (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

  24. Tomasulo Drawbacks • Complexity • delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 (in CA:AQA 2/e, before it was in silicon!) • Many associative stores (CDB) at high speed • Performance limited by Common Data Bus • Each CDB must go to multiple functional units high capacitance, high wiring density • Number of functional units that can complete per cycle limited to one! • Multiple CDBs  more FU logic for parallel assoc stores (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP

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